Firestorm: PMULL + EOR (1Q) measurements

Code:

  pmull v0.1q, v1.1d, v2.1d
  eor v0.16b, v0.16b, v3.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3f	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	map dispatch bubble (d6)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
2004	289	2	0	0	39	25	1000	1000	1000	8000	0	270	289	289	3	22	1000	2000	4000	289	289	1	1	2001	2000	0	0	136	16	286	2000	290	290	290	290	290
2004	289	2	0	0	39	25	1000	1000	1000	8000	0	270	289	289	3	22	1000	2000	4000	289	289	1	1	2001	2000	0	0	136	16	286	2000	290	290	290	290	290
2004	289	2	0	0	39	25	1000	1000	1000	8000	0	270	289	289	3	22	1000	2000	4000	289	289	1	1	2001	2000	0	6	136	16	286	2000	290	290	290	290	290
2004	289	2	0	0	39	25	1000	1000	1000	8000	0	270	289	289	3	22	1000	2000	4000	289	289	1	1	2001	2000	1	0	136	16	286	2000	290	290	290	290	290
2004	289	2	0	0	39	25	1000	1000	1000	8000	0	270	289	289	3	22	1000	2000	4000	289	289	1	1	2001	2000	0	0	136	16	286	2000	290	290	290	290	290
2004	289	2	0	0	39	25	1000	1000	1000	8000	0	270	289	289	3	22	1000	2000	4000	289	289	1	1	2001	2000	0	0	136	16	286	2000	290	290	290	290	290
2004	289	2	0	0	39	25	1000	1000	1000	8000	0	270	289	289	3	22	1000	2000	4000	289	289	1	1	2001	2000	0	0	136	16	286	2000	290	290	290	290	290
2004	289	2	0	0	39	25	1000	1000	1000	8000	0	270	289	289	3	22	1000	2000	4000	289	289	1	1	2001	2000	0	0	136	16	286	2000	290	290	290	290	290
2004	289	2	0	0	39	25	1000	1000	1000	8000	0	270	289	289	3	22	1000	2000	4000	289	289	1	1	2001	2000	0	0	136	16	286	2000	290	290	290	290	290
2004	289	2	0	0	39	25	1000	1000	1000	8000	1	270	289	289	3	22	1000	2000	4000	289	289	1	1	2001	2000	0	0	136	16	286	2000	290	290	290	290	290

Test 2: Latency 1->2

Code:

  pmull v0.1q, v1.1d, v2.1d
  eor v0.16b, v0.16b, v3.16b
  mov v1.16b, v0.16b
  nop

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3c	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40204	30037	232	0	0	0	61	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	24	2610	2	16	1	1	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	233	0	0	0	61	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	57	2610	1	16	1	1	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	233	0	0	0	61	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	69	2610	1	16	1	1	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	232	0	0	0	441	29468	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	99	2610	1	16	1	1	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	233	0	0	0	61	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	27	2610	1	16	1	1	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	233	0	0	0	61	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	30	2610	1	16	1	1	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	233	0	0	0	89	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	2610	1	16	1	1	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	233	0	0	0	61	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	111	2610	1	16	1	1	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	233	0	0	0	89	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	6	2610	1	16	1	1	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	233	0	0	0	61	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	2610	1	16	1	1	29779	30000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40024	30037	225	0	61	29516	25	10010	10	10000	10	10000	50	4274045	1	30018	30037	30037	24538	3	25017	10658	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	3	0	0	2520	1	16	1	1	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	224	0	61	29516	25	10010	10	10000	10	10000	50	4274045	1	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	2	0	0	2520	1	16	1	1	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	61	29516	25	10010	10	10000	10	10000	50	4274045	1	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	2520	1	16	1	1	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	7	0	0	2520	1	16	1	1	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	1	0	0	2520	1	16	1	1	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	1	2520	1	16	1	2	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25029	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	2	0	0	2520	1	16	1	1	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	28	3	0	2520	1	16	1	1	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	241	0	189	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	2520	1	16	1	1	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	61	29516	50	10019	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30091	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	2520	1	16	1	1	29784	30000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->3

Code:

  pmull v0.1q, v1.1d, v2.1d
  eor v0.16b, v0.16b, v3.16b
  mov v2.16b, v0.16b
  nop

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40204	30037	233	0	0	0	0	12	176	61	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	0	3	24995	10100	200	0	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	2610	2	16	1	1	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	233	0	0	0	0	0	0	61	29516	25	10100	100	10000	100	10000	500	4274045	1	30018	30037	30037	24515	0	3	24995	10100	200	0	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	2610	1	16	1	1	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	233	0	0	0	0	0	0	61	29516	25	10100	100	10000	100	10000	500	4274045	1	30018	30037	30037	24515	0	3	24995	10100	204	0	30000	200	60494	30037	30037	1	1	40201	100	99	100	100	30000	100	0	2	0	0	2642	1	16	1	1	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	233	0	0	0	0	0	0	61	29516	25	10100	100	10000	100	10000	500	4274045	1	30018	30037	30037	24515	0	3	24995	10100	200	0	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	2610	1	16	1	1	29779	1	30000	100	30038	30038	30038	30038	30038
40204	30037	233	0	0	0	0	0	0	61	29516	25	10100	100	10000	100	10000	500	4274045	1	30018	30037	30037	24515	0	3	24995	10100	200	0	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	2610	1	16	1	1	29779	0	30000	100	30038	30038	30038	30149	30038
40204	30037	233	0	0	0	0	0	0	2252	29410	25	10122	102	10018	108	10150	500	4274045	1	30018	30037	30037	24498	0	3	24995	10100	200	0	30247	202	61492	30147	30145	1	1	40201	100	99	100	100	30000	100	0	0	0	0	2610	1	16	1	1	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	232	0	0	0	0	0	0	61	29516	25	10100	100	10000	100	10000	500	4274045	1	30018	30037	30037	24515	0	3	24995	10100	200	0	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	2610	1	16	1	1	29779	0	30000	100	30038	30094	30038	30038	30092
40204	30147	232	0	0	0	0	0	0	61	29516	25	10100	100	10000	100	10000	500	4274045	1	30018	30037	30037	24515	0	3	24995	10100	200	0	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	2610	1	16	1	1	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	232	0	0	0	0	0	0	61	29516	25	10100	100	10000	100	10000	500	4274045	1	30018	30037	30037	24515	0	3	24995	10100	200	0	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	2610	1	16	1	1	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	232	0	0	0	0	0	0	61	29516	25	10100	100	10000	100	10000	500	4274045	1	30018	30037	30037	24515	0	3	24995	10100	200	0	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	2610	1	16	1	1	29779	0	30000	100	30260	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40024	30037	241	0	0	0	287	29516	25	10010	10	10000	10	10000	50	4274045	1	30018	0	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	2520	0	4	16	3	4	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	0	0	61	29516	25	10010	10	10000	10	10000	50	4274045	1	30018	0	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	2520	0	4	16	4	3	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	0	0	61	29516	25	10010	10	10000	10	10000	50	4274045	1	30018	0	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	2520	0	4	16	2	4	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	0	0	61	29516	25	10010	10	10000	10	10000	50	4274045	1	30018	0	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	2520	0	4	16	6	5	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	0	0	61	29516	25	10010	10	10000	10	10000	50	4274045	1	30018	0	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	2520	0	6	16	4	3	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	0	0	61	29516	25	10010	10	10000	10	10000	50	4274045	1	30018	0	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	2520	0	4	16	4	3	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	0	0	536	29516	25	10010	10	10009	10	10000	50	4274045	1	30018	0	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	2520	0	3	16	4	4	29784	30000	10	30038	34270	30038	30038	30038
40024	30037	225	0	0	0	61	29516	25	10010	10	10000	10	10000	50	4272279	1	30018	0	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	2520	0	3	16	4	4	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	0	0	61	29516	25	10010	10	10000	10	10000	50	4274045	1	30018	0	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	2520	0	3	16	3	4	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	0	0	61	29516	25	10010	10	10000	10	10000	50	4274045	1	30018	0	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	2520	0	4	16	4	3	29784	30000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->4

Code:

  pmull v0.1q, v1.1d, v2.1d
  eor v0.16b, v0.16b, v3.16b
  mov v3.16b, v0.16b
  nop

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40204	30037	233	0	0	12	103	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	0	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	2610	2	16	1	1	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	232	0	0	0	61	29516	25	10100	100	10000	100	10000	500	4274045	1	30018	0	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	2610	1	16	1	1	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	233	0	0	27	103	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	0	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	42	0	2610	1	16	1	1	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	233	0	0	0	82	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	0	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	2610	1	16	1	1	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	233	0	0	0	61	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	0	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	2610	1	16	1	1	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	233	0	0	0	103	29516	25	10100	100	10000	100	10000	500	4274045	1	30018	0	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	2610	1	16	1	1	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	233	0	0	0	89	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	0	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	2610	1	16	1	1	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	233	0	0	0	61	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	0	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	6	0	2610	1	16	1	1	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	232	0	0	0	61	29516	25	10100	100	10000	100	10000	500	4274045	1	30018	0	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	2610	1	16	1	1	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	232	0	0	0	103	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	0	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	2610	1	16	1	1	29779	30000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40024	30037	225	0	0	0	0	0	0	2	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	2	3	0	2525	16	16	13	12	29784	30000	10	30038	30038	30038	30038	30038
40025	30037	245	1	0	0	0	0	0	1	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	3	0	0	0	2525	12	16	11	9	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	1	0	0	0	0	0	1	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	0	2527	15	16	13	14	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	1	0	0	0	0	0	1	64	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	41	0	132	0	2525	13	16	13	15	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	224	1	0	0	0	0	0	1	64	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	26	0	6	0	2526	13	16	11	14	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	1	0	0	0	0	0	1	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	1	0	75	0	2525	9	16	14	15	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	1	0	0	0	0	0	1	61	29516	25	10010	10	10000	10	10000	50	3906905	0	30018	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	0	2526	13	16	10	15	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	239	1	0	0	0	0	0	1	943	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	0	2526	17	16	10	13	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	1	0	0	0	0	0	1	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	0	2526	12	16	11	18	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	1	0	0	0	0	0	1	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	0	2526	11	16	15	14	29784	30000	10	30038	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  pmull v0.1q, v8.1d, v9.1d
  eor v0.16b, v0.16b, v10.16b
  pmull v1.1q, v8.1d, v9.1d
  eor v1.16b, v1.16b, v10.16b
  pmull v2.1q, v8.1d, v9.1d
  eor v2.16b, v2.16b, v10.16b
  pmull v3.1q, v8.1d, v9.1d
  eor v3.16b, v3.16b, v10.16b
  pmull v4.1q, v8.1d, v9.1d
  eor v4.16b, v4.16b, v10.16b
  pmull v5.1q, v8.1d, v9.1d
  eor v5.16b, v5.16b, v10.16b
  pmull v6.1q, v8.1d, v9.1d
  eor v6.16b, v6.16b, v10.16b
  pmull v7.1q, v8.1d, v9.1d
  eor v7.16b, v7.16b, v10.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0f	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20065	155	0	285	39	25	80100	100	80000	100	80000	500	640000	0	0	20045	0	20064	20064	0	3	141	80100	200	160000	200	320000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	3	0	0	0	10111	1	16	2	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	156	0	351	39	25	80100	100	80000	100	80000	500	640000	0	0	20045	0	20064	20064	0	3	22	80100	200	160000	200	320000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10111	2	16	1	2	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	156	0	345	39	25	80100	100	80000	100	80000	500	640000	0	0	20045	0	20064	20064	0	3	22	80100	200	160000	200	320000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10112	2	16	2	2	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	156	0	375	39	25	80100	100	80000	100	80000	500	640000	0	0	20045	0	20064	20064	0	3	22	80100	200	160000	200	320000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10112	2	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	155	0	396	39	25	80100	100	80000	100	80000	500	640000	0	0	20045	3	20064	20064	0	3	22	80100	200	160000	200	320000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10111	2	16	2	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	161	0	321	39	25	80100	100	80000	100	80000	500	640000	0	0	20045	0	20064	20064	0	18	22	80100	200	160000	200	320000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10111	1	16	1	2	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	155	0	0	39	25	80100	100	80000	100	80000	500	640000	0	0	20045	0	20064	20064	0	3	22	80100	200	160000	200	320000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10111	2	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	156	0	504	39	25	80100	100	80000	100	80000	500	640000	0	0	20045	0	20064	20064	0	3	22	80100	200	160000	200	320000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10112	3	16	1	2	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	156	0	357	39	25	80100	100	80000	100	80000	500	640000	0	0	20045	0	20064	20064	0	3	22	80100	200	160000	200	320000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	3	0	0	0	10112	1	16	1	2	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	156	0	282	102	25	80100	100	80000	100	80000	500	640000	0	0	20045	0	20064	20064	0	3	22	80100	200	160000	200	320000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10112	1	16	1	2	20061	160000	100	20065	20065	20065	20065	20065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20064	155	1	0	0	114	25	80010	10	80000	10	80000	50	640000	1	1	20027	20046	20046	3	22	80010	20	160000	20	320000	20046	20304	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10043	3	1	1	21	24	6	2	2	17	18	20047	15	0	0	160000	10	20051	20051	20051	20051	20051
160024	20046	156	0	0	0	45	25	80010	10	80000	10	80000	50	640000	0	1	20031	20050	20050	3	22	80010	20	160000	20	320000	20050	20273	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10042	3	1	2	18	20	6	1	2	20	19	20047	30	0	0	160000	10	20047	20051	20051	20047	20051
160024	20050	156	0	0	0	51	25	80010	10	80000	10	80000	50	640000	0	1	20027	20046	20050	3	22	80010	20	160000	20	320000	20050	20258	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10043	3	1	2	17	24	6	2	2	17	17	20047	30	0	0	160000	10	20051	20051	20051	20052	20051
160024	20046	155	0	0	0	182	25	80010	10	80000	10	80000	50	640000	1	1	20031	20107	20046	3	22	80010	20	160000	20	320000	20046	20250	1	1	160021	10	9	10	10	160000	10	0	0	0	3	10039	3	2	2	12	24	4	2	2	17	17	20048	30	0	0	160000	10	20047	20051	20047	20047	20047
160024	20050	156	0	12	0	450	25	80010	10	80000	10	80000	50	640000	1	1	20027	20050	20046	3	22	80010	20	160000	20	320000	20052	20258	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10042	3	1	2	17	24	10	2	3	20	14	20048	20	0	1	160000	10	20052	20052	20062	20052	20052
160024	20051	156	0	0	0	45	29	80010	10	80000	10	80000	50	640000	1	1	20032	20051	20051	3	22	80010	20	160000	20	320000	20051	20288	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10043	3	1	1	19	25	4	1	1	16	17	20048	20	0	1	160000	10	20052	20052	20052	20052	20052
160024	20051	155	0	0	1	45	27	80010	10	80000	10	80000	50	640000	1	1	20032	20051	20051	3	22	80010	20	160000	20	320000	20051	20250	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10039	6	1	1	16	25	6	2	2	17	19	20061	40	0	2	160000	10	20061	20061	20061	20061	20061
160024	20051	156	0	0	0	45	27	80010	10	80000	10	80000	50	640000	1	1	20032	20051	20051	3	22	80010	20	160000	20	320000	20051	20267	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10038	3	1	1	18	25	4	1	1	17	19	20048	20	0	2	160000	10	20052	20065	20052	20052	20052
160024	20051	155	0	0	0	45	27	80010	10	80000	10	80000	50	640000	1	1	20032	20051	20051	3	22	80010	20	160000	20	320000	20051	20263	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10046	3	1	2	19	25	4	1	1	17	17	20048	20	0	1	160000	10	20061	20061	20052	20052	20061
160024	20060	155	0	0	0	51	29	80010	10	80000	10	80000	50	640000	1	1	20032	20060	20051	3	22	80010	20	160000	20	320000	20060	20276	1	1	160021	10	9	10	10	160000	10	0	0	0	3	10038	3	1	1	16	25	4	1	1	17	16	20048	20	0	1	160000	10	20052	20052	20052	20052	20052

PMULL + EOR (1Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations