Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PMULL + EOR (8H)

Test 1: uops

Code:

  pmull v0.8h, v1.8b, v2.8b
  eor v0.16b, v0.16b, v3.16b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e373a3f51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
200428920015025161010001000800012702892890322100020004000289289112001200000137216112862000290290290290290
20042892060404525100010001000800002702892890322100020004000289289112001200000138216222862000290290290290290
200428920003925100010001000800012702892890322100020004000289289112001200000137116112862000290290290290290
200428930003925100010001000800002702892890322100020004000289289112001200000140116112862000290290290290290
200428920003925100010001000800002702892890322100020004000289289112001200000137116112862000290290290290290
200428920006725100010001000800012702892890322100020004000289289112001200000137116212862000290290290290290
200428920003925100010001000800012702892890322100020004000289289112001200000137116112862000290290290290290
200428920004525100010001000800012702892890322100020004000289289112001200000137116112862000290290290290290
200428920003925100010001000800012702892890322100020004000289289112001200020137116222862000290290290290290
200428930004825100010001000800012702892890322100020004000289289112001200000137116112862000290290290290290

Test 2: Latency 1->2

Code:

  pmull v0.8h, v1.8b, v2.8b
  eor v0.16b, v0.16b, v3.16b
  mov v1.16b, v0.16b
  nop
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
402043003723310100002165429516251010010010000100100005004274045030018300373003724515032499510100200300002006000030037300371140201100991001003000010000000000261441653297790300001003003830038300383003830038
4020430037232101203453961125929516251010010010000100100005004274045030018300373003724515032499510100200300002006000030037300371140201100991001003000010000000000261531655297790300001003003830038300383003830038
402043003723310100001119129516251010010010000100100005004274045030018300373003724515032499510100200300002006000030037300371140201100991001003000010000000000261451666297790300001003003830038300383003830038
40204300372331010000111029516251010010010000100100005004274045030018300373003724515032499510100200300002006000030037300371140201100991001003000010000000000261451635297790300001003003830038300383003830038
40204300372331010000116629516251010010010000100100005004274045030018300373003724515032499510100200300002006000030037300371140201100991001003000010000000000261451644297790300001003003830038300383003830038
40204300372331010000142829516251010010010000100100005004274045030018300373003724515032499510100200300002006000030037300371140201100991001003000010000000000261451644297790300001003003830038300383003830038
40204300372331010000150829516251010010010000100100005004274045030018300373003724515032499510100200300002006000030037300371140201100991001003000010000000000261441655297790300001003003830038300383003830038
40204300372331010090138429516251010010010000100100005004274045030018300373003724515032499510100200300002006000030037300371140201100991001003000010001000000261431655297790300001003003830038300383003830038
40204300372321010000198129516251010010010000100100005004274045030018300373003724515032499510100200300002006000030037300371140201100991001003000010000000000261451655297790300001003003830038300383003830038
40204300372331010090165295162510100100100001001000050042740450300183003730037245150324995101002003000020060000300373003711402011001051001003000010000001000261331653297790300001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)0e181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
40024300372320000012429516251001010100001010000504274045030018300373003724538325017100102030000206000030037300371140021109101030000100002520216222978430000103003830038300383003830038
40024300372330000011229516251001010100001010000504274045030018300373003724538325017100102030000206000030037300371140021109101030000100002520316362978430000103003830038300383003830038
40024300372330000022429516251001010100001010000504274045030018300373003724538325017100102030000206000030037300371140021109101030000100002520616222978430000103003830038300383003830038
40024300372320000050429516251001010100001010000504274045030018300373003724538325017100102030000206000030037300371140021109101030000100002520216622978430000103003830038300383003830038
400243003723300970126129516251001010100001010000504274045030018300373003724538325017100102030000206000030037300371140021109101030000100002520216262978430000103003830038300383003830038
4002430037233000006129516251001010100001010000504274045030018300373003724538325017100102030000206000030037300371140021109101030000100202520216222978430000103003830038300383003830038
40024300372330000126129516251001010100001010000504274045030018300373003724538325017100102030000206000030037300371140021109101030000100102520616622978430000103003830038300383003830038
4002430037233000006129516251001010100001010000504274045030018300373003724538325017100102030000206000030037300371140021109101030000100002520316362978430000103003830038300383003830038
40024300372330000014929516251001010100001010000504274045030018300373003724538325017100102030000206000030037300371140021109101030000100002520216622978430000103003830038300383003830038
4002430037233000006129516251001010100001010000504274045030018300373003724538325017100102030000206000030037300371140021109101030000100032520216362978430000103003830038300383003830038

Test 3: Latency 1->3

Code:

  pmull v0.8h, v1.8b, v2.8b
  eor v0.16b, v0.16b, v3.16b
  mov v2.16b, v0.16b
  nop
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
4020430037233309612951625101001001000010010000500427404503001830037300372451532499510100200300002006000030037300371140201100991001003000010000000261021611297790300001003003830038300383003830038
4020430037233468892951625101001001000010010000500427404503001830037300372451532499510100200300002006000030037300371140201100991001003000010000000261011611297790300001003003830038300383003830038
4020430037233381612951625101001001000010010000500427404503001830037300372451532499510100200300002006000030037300371140201100991001003000010000000261011611297790300001003003830038300383003830038
4020430037233477612951625101001001000010010000500427404513001830037300372451532499510100200300002006000030037300371140201100991001003000010000000261011611297790300001003003830038300383003830038
40204300372334411032951625101001001000010010000500427404513001830037300372451532499510100200300002006000030037300371140201100991001003000010001030261011622297790300001003003830038300383003830038
402043003723342612951625101001001000010010000500427404503001830037300372451532499510100200300002006000030037300371140201100991001003000010000030261011611297790300001003003830038300383003830038
4020430037242501612951625101001001000010010000500427404513001830037300372451532499510100200300002006000030037300371140201100991001003000010000030261011611297790300001003003830038300383003830038
4020430037233591612951625101001001000010010000500427404503001830037300372451532499510100200300002006000030037300371140201100991001003000010000000261011611297790300001003003830038300383003830038
40204300372320612951625101001001000010010000500427404513001830037300372451532499510100200300002006000030037300371140201100991001003000010000030261011611297790300001003003830038300383003830038
4020430037233399612951625101001001000010010000500427404503001830037300372451532499510100200300002006000030037300371140201100991001003000010000000261011611297790300001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)0e1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
40024300372240230612951625100101010000101000050427404503001830037300372453832501710010203000020600003003730037114002110910103000010000002520416432978430000103003830038300383003830038
40024300372250030612951625100101010000101000050427404503001830037300372453832501710010203000020600003003730037114002110910103000010000002520316242978430000103003830038300383003830038
40024300372240015612951625100101010000101000050427404513001830037300372453832501710010203000020600003003730037114002110910103000010000002520416222978430000103009430038300383003830038
4002430037238000612951625100101010000101000050427404503001830037300372453832501710010203000020600003003730037114002110910103000010000002520416422978430000103003830038300383009230038
4002430037225000612951625100101010000101000050427404503001830037300372453832501710010203000020600003003730037114002110910103000010000002520216332978430000103003830038300383003830038
40024300372250015612951625100101010000101000050427404503001830037300372453832501710010203000020600003003730037114002110910103000010000002520416222978430000103003830038300383003830038
4002430037225000612951625100101010000101000050427404503001830037300372453832501710010203000020600003003730037114002110910103000010000002520316442978430000103003830038300383003830038
4002430037225000822951625100101010000101000050427404503001830037300372453832501710010203000020600003003730037114002110910103000010000002520416242978430000103003830038300383003830038
400243003722500211452951625100101010000101000050427404503001830037300372453832501710010203000020600003003730037114002110910103000010000002520416442978430000103003830038300383003830038
40024300372250090612951625100101010000101000050427404503001830037300372453832501710010203000020600003003730037114002110910103000010000002520416622978430000103003830038300383003830038

Test 4: Latency 1->4

Code:

  pmull v0.8h, v1.8b, v2.8b
  eor v0.16b, v0.16b, v3.16b
  mov v3.16b, v0.16b
  nop
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
4020430037233101000261018829516251010010010091100100005004274045030018300373003724515027249951010020030000200600003003730037114020110099100100300001000000026145163529779300001003026130038300383003830038
40204300372331010000016529516183101001001000010010000500427404503001830037300372451503249951010020030000200600003003730037114020110099100100300001000000026145165529779300001003003830038300383003830038
4020430037233101000001652951625101001001000010010000533427404513001830037300372451503249951010020030000200615303003730037114020110099100100300001000000026145166629779300001003003830038300383003830038
4020430037232111000001652951625101001001000010010000500427404513001830037301482451503249951010020030000200600003003730037114020110099100100300001000000326875165329779300001003003830038300383003830038
4020430037233101000001652951625101001001000010010000500427404503001830037300372451503249951010020030000200600003003730037114020110099100100300001000001026143163529848300001003003830038300383003830038
4020430037232101000001652897625101001001000010010000500427404503001830037300372451503249951010020030000200600003003730037114020110099100100300001000000026143164429779300001003003828596300383003830038
4020430037233101000001652951625101001001000010010000500427404513001830037300372451503249951010020030000200600003003730037114020110099100100300001000001026149165329779300001003003830038300383003830038
4020430037241101000001652951625101001001000010010000500427404503001830037300372451503249951076720030000200600003003730037114020110099100100300001000000026135165529779300001003003830038300383003830038
4020430037233101000001652951625101001001000010010000500427404513001830037300372451503249951010020030000200600003003730037114020110099100100300001000000026134165529779300001003003830038300383003830038
4020430037233101000001652951625101001001000010010000500427404503001830037300372451503249951010020030000200600003003730037114020110099100100300001000000026143164529779300001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9aaacc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
4002430037225000000612951625100101010000101000050426451703001830037300372453803250171001020300002060000300373003711400211091010300001000000025201161129784130000103009430038300383003830592
400243059722941101013208806627271662131056610110141211674614170034030373305953053822017220413025076118452032378206509830312305891114002110910103000010313028125427471161129784030000103003830038300383009530038
400243003723301004807702951625100101010000101000050427404513001830037300372453803250171001020300002060000300373003711400211091010300001000009025201171129784030000103003830038300383003830038
4002430037225000000612951625100101010000101000050427404513007730037300372453803250171001020300002060000300373003711400211091010300001000000025201161129784030000103003830038300383003830038
4002430037225000000124295162510010101000010100005042740450300183003730094245382393250171050920300002060000300923003711400211091010300001000000025201321129823030000103014830038300383009330038
4002430037225000000612951625100101010000101000050427404503001830037300372453803250171001020300002060000300373003711400211091010300001000000025201161129784030000103003830038300383003830038
40024300372250000001032951625100101010000101000050427404503001830037300372453803250171001020300002060000300373003711400211091010300001000000025201161229784030000103003830038300383003830038
40024300372250000001032951625100101010000101000050427404513001830037300372453803250171001020300002060000300373003711400211091010300001000000025201161129784030000103003830038300383003830038
4002430037225000000612951625100101010000101000050427404513001830037300372453803250171001020300002060000300373003711400211091010300001001003025201161229784030000103003830038300943003830038
40024300372350000088612951625100101010000101000050427404503001830037300372453803250171001020307662060000300943009111400211091010300001000006025201161129784030000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  pmull v0.8h, v8.8b, v9.8b
  eor v0.16b, v0.16b, v10.16b
  pmull v1.8h, v8.8b, v9.8b
  eor v1.16b, v1.16b, v10.16b
  pmull v2.8h, v8.8b, v9.8b
  eor v2.16b, v2.16b, v10.16b
  pmull v3.8h, v8.8b, v9.8b
  eor v3.16b, v3.16b, v10.16b
  pmull v4.8h, v8.8b, v9.8b
  eor v4.16b, v4.16b, v10.16b
  pmull v5.8h, v8.8b, v9.8b
  eor v5.16b, v5.16b, v10.16b
  pmull v6.8h, v8.8b, v9.8b
  eor v6.16b, v6.16b, v10.16b
  pmull v7.8h, v8.8b, v9.8b
  eor v7.16b, v7.16b, v10.16b
  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042006515600392580100100800001008000050064000012004520064200643228010020016000020032000020064200641116020110099100100160000100018010111116112006101600001002006520065200652006520065
160204200641560639258010010080000100800005006400001200452006420064322801002001600002003200002006420064111602011009910010016000010000010111116112006101600001002006520065200652006520065
1602042006415600392580100100800001008000050064000012004520064200643228010020016000020032000020064200641116020110099100100160000100018010111116112006101600001002006520065200652006520065
16020420064155003925801001008000010080000500640000020045200642006432280100200160000200320000200642006411160201100991001001600001000168010111116112006101600001002006520065200652006520065
1602042006415600392580100100800001008000050064000012004520064200643228010020016000020032000020064200641116020110099100100160000100018010111116112006101600001002006520065200652006520065
16020420064156003925801001008000010080000500640000020045200642006432280100200160000200320000200642006411160201100991001001600001000120010111116112006101600001002006520065200652006520065
160204200641550124852580100100800001008000050064000002004520064200643228010020016000020032000020122200641116020110099100100160000100018010111116112006101600001002006520065200652006520065
160204200641560081258010010080000100800005006400001200452006420064322801002001600002003200002006420064111602011009910010016000010000010111116112006101600001002006520065200652006520065
160204200641560081258010010080000100800005006400000200452006420064322801002001600002003200002006420064111602011009910010016000010000010111116112006101600001002006520065200652006520065
1602042006415500392580100100800001008000050064000002004520064200643228010020016000020032000020064200641116020110099100100160000100018010111116112006101600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03l1i tlb fill (04)l2 tlb miss data (0b)3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200581501045258001010800001080000506400001120027200462004632280010201600002032000020046200461116002110910101600001000001002731122021123200431500160000102004720047200472004720047
160024200461510045258001010800001080000506400000120027200462004632280010201600002032000020046200461116002110910101600001000001002631132021132200431500160000102004720047200472004720047
160024200461500045258001010800001080000506400001120027200462004632280010201600002032000020046200461116002110910101600001000001002731132021133200431500160000102004720047200472004720047
160024200461500045258001010800001080000506400001120027200462004632280010201600002032000020046200461116002110910101600001000001002631132021133200431500160000102004720047200472004720047
160024200461500045258001010800001080000506400001120027200462004632280010201600002032000020046200461116002110910101600001000001002531132021133200431500160000102004720051200472004720051
160024200501500045258001010800001080000506400001120027200462004632280010201600002032000020046200461116002110910101600001000001002631132021133200431500160000102004720047200472004720047
160024200461500045258001010800001080000506400001120027200462004632280010201600002032000020046200461116002110910101600001000001002962242442232200473000160000102005120051200512005120051
1600242005015000621258001010800001080000506400000120027200462004632280010201600002032000020046200461116002110910101600001000301002531132021133200431500160000102004720047200472004720047
160024200461500045258001010800001080000506400001120027200462004632280010201600002032000020046200461116002110910101600001000001002531132021146200431500160000102005120047200472005120047
160024200461500045258001010800001080000506400001120027200462004632280010201600002032000020050200461116002110910101600001000001002631132021233200471500160000102004720051200472005120051