Firestorm: PMULL + EOR (8H) measurements

Code:

  pmull v0.8h, v1.8b, v2.8b
  eor v0.16b, v0.16b, v3.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3a	3f	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
2004	289	2	0	0	1	50	25	1610	1000	1000	8000	1	270	289	289	0	3	22	1000	2000	4000	289	289	1	1	2001	2000	0	0	137	2	16	1	1	286	2000	290	290	290	290	290
2004	289	2	0	604	0	45	25	1000	1000	1000	8000	0	270	289	289	0	3	22	1000	2000	4000	289	289	1	1	2001	2000	0	0	138	2	16	2	2	286	2000	290	290	290	290	290
2004	289	2	0	0	0	39	25	1000	1000	1000	8000	1	270	289	289	0	3	22	1000	2000	4000	289	289	1	1	2001	2000	0	0	137	1	16	1	1	286	2000	290	290	290	290	290
2004	289	3	0	0	0	39	25	1000	1000	1000	8000	0	270	289	289	0	3	22	1000	2000	4000	289	289	1	1	2001	2000	0	0	140	1	16	1	1	286	2000	290	290	290	290	290
2004	289	2	0	0	0	39	25	1000	1000	1000	8000	0	270	289	289	0	3	22	1000	2000	4000	289	289	1	1	2001	2000	0	0	137	1	16	1	1	286	2000	290	290	290	290	290
2004	289	2	0	0	0	67	25	1000	1000	1000	8000	1	270	289	289	0	3	22	1000	2000	4000	289	289	1	1	2001	2000	0	0	137	1	16	2	1	286	2000	290	290	290	290	290
2004	289	2	0	0	0	39	25	1000	1000	1000	8000	1	270	289	289	0	3	22	1000	2000	4000	289	289	1	1	2001	2000	0	0	137	1	16	1	1	286	2000	290	290	290	290	290
2004	289	2	0	0	0	45	25	1000	1000	1000	8000	1	270	289	289	0	3	22	1000	2000	4000	289	289	1	1	2001	2000	0	0	137	1	16	1	1	286	2000	290	290	290	290	290
2004	289	2	0	0	0	39	25	1000	1000	1000	8000	1	270	289	289	0	3	22	1000	2000	4000	289	289	1	1	2001	2000	2	0	137	1	16	2	2	286	2000	290	290	290	290	290
2004	289	3	0	0	0	48	25	1000	1000	1000	8000	1	270	289	289	0	3	22	1000	2000	4000	289	289	1	1	2001	2000	0	0	137	1	16	1	1	286	2000	290	290	290	290	290

Test 2: Latency 1->2

Code:

  pmull v0.8h, v1.8b, v2.8b
  eor v0.16b, v0.16b, v3.16b
  mov v1.16b, v0.16b
  nop

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40204	30037	233	1	0	1	0	0	0	0	2	1654	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	0	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	2614	4	16	5	3	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	232	1	0	1	2	0	345	396	1	1259	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	0	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	2615	3	16	5	5	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	233	1	0	1	0	0	0	0	1	1191	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	0	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	2614	5	16	6	6	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	233	1	0	1	0	0	0	0	1	110	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	0	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	2614	5	16	3	5	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	233	1	0	1	0	0	0	0	1	166	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	0	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	2614	5	16	4	4	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	233	1	0	1	0	0	0	0	1	428	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	0	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	2614	5	16	4	4	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	233	1	0	1	0	0	0	0	1	508	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	0	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	2614	4	16	5	5	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	233	1	0	1	0	0	9	0	1	384	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	0	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	1	0	0	0	0	0	0	2614	3	16	5	5	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	232	1	0	1	0	0	0	0	1	981	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	0	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	2614	5	16	5	5	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	233	1	0	1	0	0	9	0	1	65	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	0	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	105	100	100	30000	100	0	0	0	0	1	0	0	0	2613	3	16	5	3	29779	0	30000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	0e	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40024	30037	232	0	0	0	0	0	124	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	2520	2	16	2	2	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	233	0	0	0	0	0	112	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	2520	3	16	3	6	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	233	0	0	0	0	0	224	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	2520	6	16	2	2	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	232	0	0	0	0	0	504	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	2520	2	16	6	2	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	233	0	0	97	0	12	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	2520	2	16	2	6	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	233	0	0	0	0	0	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	2	0	2520	2	16	2	2	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	233	0	0	0	0	12	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	1	0	2520	6	16	6	2	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	233	0	0	0	0	0	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	2520	3	16	3	6	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	233	0	0	0	0	0	149	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	2520	2	16	6	2	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	233	0	0	0	0	0	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	3	2520	2	16	3	6	29784	30000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->3

Code:

  pmull v0.8h, v1.8b, v2.8b
  eor v0.16b, v0.16b, v3.16b
  mov v2.16b, v0.16b
  nop

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40204	30037	233	309	61	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	0	2610	2	16	1	1	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	233	468	89	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	0	2610	1	16	1	1	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	233	381	61	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	0	2610	1	16	1	1	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	233	477	61	29516	25	10100	100	10000	100	10000	500	4274045	1	30018	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	0	2610	1	16	1	1	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	233	441	103	29516	25	10100	100	10000	100	10000	500	4274045	1	30018	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	1	0	3	0	2610	1	16	2	2	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	233	42	61	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	3	0	2610	1	16	1	1	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	242	501	61	29516	25	10100	100	10000	100	10000	500	4274045	1	30018	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	3	0	2610	1	16	1	1	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	233	591	61	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	0	2610	1	16	1	1	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	232	0	61	29516	25	10100	100	10000	100	10000	500	4274045	1	30018	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	3	0	2610	1	16	1	1	29779	0	30000	100	30038	30038	30038	30038	30038
40204	30037	233	399	61	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	0	2610	1	16	1	1	29779	0	30000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	0e	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40024	30037	224	0	2	30	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	2520	4	16	4	3	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	0	30	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	2520	3	16	2	4	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	224	0	0	15	61	29516	25	10010	10	10000	10	10000	50	4274045	1	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	2520	4	16	2	2	29784	30000	10	30094	30038	30038	30038	30038
40024	30037	238	0	0	0	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	2520	4	16	4	2	29784	30000	10	30038	30038	30038	30092	30038
40024	30037	225	0	0	0	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	2520	2	16	3	3	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	0	15	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	2520	4	16	2	2	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	0	0	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	2520	3	16	4	4	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	0	0	82	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	2520	4	16	2	4	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	0	21	145	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	2520	4	16	4	4	29784	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	0	90	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	2520	4	16	6	2	29784	30000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->4

Code:

  pmull v0.8h, v1.8b, v2.8b
  eor v0.16b, v0.16b, v3.16b
  mov v3.16b, v0.16b
  nop

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40204	30037	233	1	0	1	0	0	0	261	0	1	88	29516	25	10100	100	10091	100	10000	500	4274045	0	30018	30037	30037	24515	0	27	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	0	2614	5	16	3	5	29779	30000	100	30261	30038	30038	30038	30038
40204	30037	233	1	0	1	0	0	0	0	0	1	65	29516	183	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	0	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	0	2614	5	16	5	5	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	233	1	0	1	0	0	0	0	0	1	65	29516	25	10100	100	10000	100	10000	533	4274045	1	30018	30037	30037	24515	0	3	24995	10100	200	30000	200	61530	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	0	2614	5	16	6	6	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	232	1	1	1	0	0	0	0	0	1	65	29516	25	10100	100	10000	100	10000	500	4274045	1	30018	30037	30148	24515	0	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	3	2687	5	16	5	3	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	233	1	0	1	0	0	0	0	0	1	65	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	0	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	1	0	2614	3	16	3	5	29848	30000	100	30038	30038	30038	30038	30038
40204	30037	232	1	0	1	0	0	0	0	0	1	65	28976	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	0	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	0	2614	3	16	4	4	29779	30000	100	30038	28596	30038	30038	30038
40204	30037	233	1	0	1	0	0	0	0	0	1	65	29516	25	10100	100	10000	100	10000	500	4274045	1	30018	30037	30037	24515	0	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	1	0	2614	9	16	5	3	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	241	1	0	1	0	0	0	0	0	1	65	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	0	3	24995	10767	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	0	2613	5	16	5	5	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	233	1	0	1	0	0	0	0	0	1	65	29516	25	10100	100	10000	100	10000	500	4274045	1	30018	30037	30037	24515	0	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	0	2613	4	16	5	5	29779	30000	100	30038	30038	30038	30038	30038
40204	30037	233	1	0	1	0	0	0	0	0	1	65	29516	25	10100	100	10000	100	10000	500	4274045	0	30018	30037	30037	24515	0	3	24995	10100	200	30000	200	60000	30037	30037	1	1	40201	100	99	100	100	30000	100	0	0	0	0	0	2614	3	16	4	5	29779	30000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	aa	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40024	30037	225	0	0	0	0	0	0	61	29516	25	10010	10	10000	10	10000	50	4264517	0	30018	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	0	2520	1	16	1	1	29784	1	30000	10	30094	30038	30038	30038	30592
40024	30597	229	4	1	10	10	1320	880	6627	27166	213	10566	10	11014	12	11674	61	4170034	0	30373	30595	30538	22017	2204	130	25076	11845	20	32378	20	65098	30312	30589	11	1	40021	10	9	10	10	30000	10	3	1	3	0	28125	4	2747	1	16	1	1	29784	0	30000	10	30038	30038	30038	30095	30038
40024	30037	233	0	1	0	0	48	0	770	29516	25	10010	10	10000	10	10000	50	4274045	1	30018	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	9	0	2520	1	17	1	1	29784	0	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	0	0	0	0	0	61	29516	25	10010	10	10000	10	10000	50	4274045	1	30077	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	0	2520	1	16	1	1	29784	0	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	0	0	0	0	0	124	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30094	24538	239	3	25017	10509	20	30000	20	60000	30092	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	0	2520	1	32	1	1	29823	0	30000	10	30148	30038	30038	30093	30038
40024	30037	225	0	0	0	0	0	0	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	0	2520	1	16	1	1	29784	0	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	0	0	0	0	0	103	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	0	2520	1	16	1	2	29784	0	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	0	0	0	0	0	103	29516	25	10010	10	10000	10	10000	50	4274045	1	30018	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	0	0	0	0	0	2520	1	16	1	1	29784	0	30000	10	30038	30038	30038	30038	30038
40024	30037	225	0	0	0	0	0	0	61	29516	25	10010	10	10000	10	10000	50	4274045	1	30018	30037	30037	24538	0	3	25017	10010	20	30000	20	60000	30037	30037	1	1	40021	10	9	10	10	30000	10	0	1	0	0	3	0	2520	1	16	1	2	29784	0	30000	10	30038	30038	30094	30038	30038
40024	30037	235	0	0	0	0	0	88	61	29516	25	10010	10	10000	10	10000	50	4274045	0	30018	30037	30037	24538	0	3	25017	10010	20	30766	20	60000	30094	30091	1	1	40021	10	9	10	10	30000	10	0	0	0	0	6	0	2520	1	16	1	1	29784	0	30000	10	30038	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  pmull v0.8h, v8.8b, v9.8b
  eor v0.16b, v0.16b, v10.16b
  pmull v1.8h, v8.8b, v9.8b
  eor v1.16b, v1.16b, v10.16b
  pmull v2.8h, v8.8b, v9.8b
  eor v2.16b, v2.16b, v10.16b
  pmull v3.8h, v8.8b, v9.8b
  eor v3.16b, v3.16b, v10.16b
  pmull v4.8h, v8.8b, v9.8b
  eor v4.16b, v4.16b, v10.16b
  pmull v5.8h, v8.8b, v9.8b
  eor v5.16b, v5.16b, v10.16b
  pmull v6.8h, v8.8b, v9.8b
  eor v6.16b, v6.16b, v10.16b
  pmull v7.8h, v8.8b, v9.8b
  eor v7.16b, v7.16b, v10.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20065	156	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	160000	200	320000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	18	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	156	0	6	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	160000	200	320000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	156	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	160000	200	320000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	18	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	155	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	160000	200	320000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	168	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	156	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	160000	200	320000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	18	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	156	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	160000	200	320000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	120	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	155	0	12	485	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	160000	200	320000	20122	20064	1	1	160201	100	99	100	100	160000	100	0	18	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	156	0	0	81	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	160000	200	320000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	156	0	0	81	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	160000	200	320000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	155	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	160000	200	320000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	18	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l2 tlb miss data (0b)	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20058	150	1	0	45	25	80010	10	80000	10	80000	50	640000	1	1	20027	20046	20046	3	22	80010	20	160000	20	320000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10027	3	1	1	2	20	2	1	1	2	3	20043	15	0	0	160000	10	20047	20047	20047	20047	20047
160024	20046	151	0	0	45	25	80010	10	80000	10	80000	50	640000	0	1	20027	20046	20046	3	22	80010	20	160000	20	320000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10026	3	1	1	3	20	2	1	1	3	2	20043	15	0	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	20027	20046	20046	3	22	80010	20	160000	20	320000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10027	3	1	1	3	20	2	1	1	3	3	20043	15	0	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	20027	20046	20046	3	22	80010	20	160000	20	320000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10026	3	1	1	3	20	2	1	1	3	3	20043	15	0	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	20027	20046	20046	3	22	80010	20	160000	20	320000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10025	3	1	1	3	20	2	1	1	3	3	20043	15	0	0	160000	10	20047	20051	20047	20047	20051
160024	20050	150	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	20027	20046	20046	3	22	80010	20	160000	20	320000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10026	3	1	1	3	20	2	1	1	3	3	20043	15	0	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	20027	20046	20046	3	22	80010	20	160000	20	320000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10029	6	2	2	4	24	4	2	2	3	2	20047	30	0	0	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	621	25	80010	10	80000	10	80000	50	640000	0	1	20027	20046	20046	3	22	80010	20	160000	20	320000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	3	0	10025	3	1	1	3	20	2	1	1	3	3	20043	15	0	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	20027	20046	20046	3	22	80010	20	160000	20	320000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10025	3	1	1	3	20	2	1	1	4	6	20043	15	0	0	160000	10	20051	20047	20047	20051	20047
160024	20046	150	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	20027	20046	20046	3	22	80010	20	160000	20	320000	20050	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10026	3	1	1	3	20	2	1	2	3	3	20047	15	0	0	160000	10	20047	20051	20047	20051	20051

PMULL + EOR (8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations