Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PMUL (16B)

Test 1: uops

Code:

  pmul v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125482510001000100039831330183037303724153289510001000200030373037111001100000073316222630100030383038303830383038
100430372206125482510001000100039831330183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
100430372306125482510001000100039831330183037303724153289510001000200030373037111001100000673216222630100030383038303830383038
100430372308425482510001000100039831330183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
100430372306125482510001000100039831330183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
100430372206125482510001000100039831330183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
100430372206125482510001000100039831330183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
1004303723028725482510001000100039831330183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
100430372206125482510001000100039831330183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
100430372206125482510001000100039831330183037303724153289510001000200030373037111001100000373216222630100030383038303830383038

Test 2: Latency 1->2

Code:

  pmul v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225100006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000371011611296340100001003003830038300383013230038
1020430037225000006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000020071011611296340100001003003830038300383003830038
1020430037224000006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
1020430037225000006129548251013210010000100100005004277313300183003730037282653287631010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
1020430037225000009429548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000020071011611296340100001003003830038300383003830038
1020430037225000006129548251010010810000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000010071011611296340100001003003830038300383003830038
1020430037225000006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000010071011611296340100001003003830038300383003830038
1020430037224000006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
1020430037224000006129548251010013510000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372250000061295482510100100100001001000050042773133001830037300372826516287451010020010000200200003003730037111020110099100100100001000020071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001010640316332963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722500612954825100101010000121000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001030640316332963010000103003830038300383003830038
100243003722400612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  pmul v0.16b, v1.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722508212954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000171011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225003661295482510010101000010100006042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
100243003722400061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
100243003722400061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229693010000103003830038300383003830038
100243003722500061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730084111002110910101000010006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  pmul v0.16b, v8.16b, v9.16b
  pmul v1.16b, v8.16b, v9.16b
  pmul v2.16b, v8.16b, v9.16b
  pmul v3.16b, v8.16b, v9.16b
  pmul v4.16b, v8.16b, v9.16b
  pmul v5.16b, v8.16b, v9.16b
  pmul v6.16b, v8.16b, v9.16b
  pmul v7.16b, v8.16b, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000051102161120036800001002004020040200402004020040
802042003915004414125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
8020420039150094125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
802042003915003334125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
8020420039150004125801001008000010080000500640000020020200392003999733999780100200801032001602142003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
8020420039150094125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
8020420039150004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
8020420039150004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
8020420039150004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
802042003915005974125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150002140258001010800001080000506400001020020200392003999963100198001020800002016000020039200391180021109101080000104051850202161120036080000102004020040200402004020040
800242003915000339402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000050201161120036080000102004020040200402004020040
8002420039150000862580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050201161120036080000102004020040200402004020040
800242003915000252402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050201161120036080000102004020040200402004020040
800242003915000264402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050201161120036080000102004020040200402004020040
80024200391500024402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000050201161120036080000102004020040200402004020040
80024200391500004025800101080000108000050640000012002020039200399996310019800102080000201600002003920039118002110910108000010000502011611200366080000102004020040200402004020040
8002420039150000402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050201161120036080000102004020040200402004020040
8002420039150000402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050201161120036080000102004020040200402004020040
8002420039150000402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050201161120036080000102004020040200402004020040