Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

RAX1

Test 1: uops

Code:

  rax1 v0.2d, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716061168725100010001000264680120182037203715723189510001000200020372037111001100003373116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371636116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110001073116111787100020382038203820382038
100420371636116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715126116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  rax1 v0.2d, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000821968725101001001000010010000500284768012001802003720037184223187451010020010000200200002003720037111020110099100100100001002400007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001802003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
1020420037150100611968725101001001000010010000500284768012001802003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
10204200371500001701968725101001001000010010000500284768002001802003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
10204200371500001701968725101001001000010010000500284768002001802003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000019621968725101001001000010010000500284768002001802003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
10204200371500005451968725101001001000010010000500284768002001802003720037184223187451010020010000200200002003720037111020110099100100100001000000207101161119791100001002003820038200382003820038
10204200371500004451968725101391101000010010000500284768012001802003720037184223187451010020010000200200002003720037111020110099100100100001000001007101161119791100001002003820038200382003820038
10204200371500001491968725101001001000010010000561284768002001802003720037184253187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
10204200371500001491968725101001001000010010000500284768012001832003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003714906119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100663224221978510000102003820038200382003820038
1002420037150014519687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
1002420037150012619687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000103640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  rax1 v0.2d, v1.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000611968725101001001000010010000500284768020018200372003718429618741101002001000820020016200372003711102011009910010010000100000011171801600198020100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768020018200372003718429618741101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500001241968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500001241968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768020018200372003718422318745101002041000020020000200372003711102011009910010010000100000000071011611198570100001002003820038200382003820038
10204200371500001701968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500007261968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500003900611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006403163319785010000102003820038200382003820038
10024200371500004800611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006403163319785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006403163319785010000102003820038200382003820038
1002420037150000300841968725100101010000101000050284768012006620037200371844431876710010201000020200002003720037111002110910101000010000000006403163319785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006403163319785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006403163319785010000102003820038200382003820038
10024200371500006000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006403163319785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006403163319785010000102003820038200382003820038
10024200371500000002121968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006403163319785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006403163319785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  rax1 v0.2d, v8.2d, v9.2d
  rax1 v1.2d, v8.2d, v9.2d
  rax1 v2.2d, v8.2d, v9.2d
  rax1 v3.2d, v8.2d, v9.2d
  rax1 v4.2d, v8.2d, v9.2d
  rax1 v5.2d, v8.2d, v9.2d
  rax1 v6.2d, v8.2d, v9.2d
  rax1 v7.2d, v8.2d, v9.2d
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200481500006004025801001008000010080000500640000120019201092003899813999680100200800002001600002003820038118020110099100100800001000000000511021611200350800001002003920039200392003920039
8020420038150000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
802042003815000021061025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
802042003815000030304025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
8020420038150000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
802042003815000014704025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381500002404025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
8020420038150000004025801001008000010080000500640000120069200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
8020420038150000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381500003604025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420040150153925800101080000108000050640000200192003820038999603100188001020800002016000020038200381180021109101080000100005020001161120035080000102003920039200392003920039
800242003815003925800101080000108000050640000200192003820038999603100188001020800002016000020038200381180021109101080000100005020001161120035080000102003920039200392003920039
800242003815003925800101080000108000050640000200192003820038999603100188001020800002016000020038200381180021109101080000100005020001161120035080000102003920039200392003920039
800242003815003925800101080000108000050640000200192003820038999603100188001020800002016000020038200381180021109101080000100005020001161120035080000102003920039200392003920039
8002420038150213961802951080000108000050640000200192003820038999603100188001020800002016000020038200381180021109101080000100005020001161120035080000102003920039200392003920039
800242003815003925800101080000108000050640000200192003820038999603100188001020800002016000020038200381180021109101080000100005020001161120035080000102003920039200392003920039
800242003815003925800101080000108000050640000200192003820038999603100188001020800002016000020038200381180021109101080000100005020001161120035080000102003920039200392003920039
800242003815003925800881080000108000050640000200192003820038999603100188001020800002016000020038200381180021109101080000100005020001161120035080000102003920039200392003920039
800242003815003925800101080000108000050640000200192003820038999603100188001020800002016000020038200381180021109101080000100005020001161120035080000102003920039200392003920039
800242003815003925800101080000108000050640000200192003820038999603100188001020800002016000020038200381180021109101080000100005020311161120035080000102003920039200392003920039