Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

REV16 (vector, 16B)

Test 1: uops

Code:

  rev16 v0.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)091e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203716000611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037160006116862510001000100026452120182037203715713189510001000100020372037111001100033073116111786100020382038203820382038
10042037150060611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715000611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715000611686251000100010002645212018203720371571318951000100010002037203711100110008073116111786100020382038203820382038
1004203716000821686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150006116862510001000100026452120182037203715713189510001000100020372037111001100016073116111786100020382038203820382038
1004203715000611686251000100010002645212018203720371571318951000100010002037203711100110000373116111786100020382038203820382038
1004203715000611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715000611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  rev16 v0.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0309181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101171119791100001002003820038200382003820038
1020420037150000611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010051607101161119791100001002003820038200382003820038
10204200371500054595196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000307101161119791100001002003820038200382003820038
1020420037150001561196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000082196862510100100100001001000050028475210200182003720037184213187451010020010332200100002003720037111020110099100100100001001307103161119931100001002003820232200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
10024200371501000611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
10024200371500000611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
100242003715000030611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
10024200371500000611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100900640216221978610000102003820038200382003820038
10024200371500000611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100010640216221978610000102003820038200382003820038
10024200371500000611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000102000640216221978610000102003820038200382003820038
10024200371500000611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
10024200371500000611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
10024200371500000611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  rev16 v0.16b, v8.16b
  rev16 v1.16b, v8.16b
  rev16 v2.16b, v8.16b
  rev16 v3.16b, v8.16b
  rev16 v4.16b, v8.16b
  rev16 v5.16b, v8.16b
  rev16 v6.16b, v8.16b
  rev16 v7.16b, v8.16b
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042004815000002925801081008000810080020500640132120019200382003899770699898012020080032200800322003820038118020110099100100800001000000011151180160020035800001002014420102200392035620039
802042003815000011629258010810080008100800205006401321200192003820104998601210015802262008013720080230201032015521802011009910010080000100230254011151520160020035800001002003920039200392003920091
802042003815000002925801081008000810080020500640132020019200382003899770699898012020080032200800322003820038118020110099100100800001000000011151180160020035800001002003920039200392003920039
802042003815000002925801081008000810080020500640132120019200382003899770699898012020080032200800322003820038118020110099100100800001000000011151180160120035800001002003920039200392003920039
802042003815000002925801081008000810080020500640132020019200382003899770699898012020080032200800322003820038118020110099100100800001000000011151180160020035800001002003920039200392003920039
802042003815000002925801081008000810080020500640132020019200382003899770699898012020080032200800322003820038118020110099100100800001000000011151180160020035800001002003920039200392003920039
802042003815000002925801081008000810080020500640132120019200382003899777699898012020080032200800322003820038118020110099100100800001000000011151180160020035800001002003920242200392003920039
802042003815000002925801081008000810080020500640132120019200382003899770699898012020080032200800322003820038118020110099100100800001000000011151180160020035800001002003920039200392003920039
802042003815000002925801081008000810080020500640132020019200382003899770699898012020080032200800322003820038118020110099100100800001000000011151180160020035800001002003920039200392003920039
802042003815000002925801081008000810080020500640132020019200382003899770699898012020080032200800322003820038118020110099100100800001000000011151180160020035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)acc2cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200401502139258001010800001080000506400001520019200382003899960310018800102080000208000020038200381180021109101080000100000502050121613122003580000102003920039200392003920039
8002420038150039258001010800001080000506400001520019200382003899960310018800102080000208000020038200381180021109101080000100030502050121613122003580000102003920039200392003920039
80024200381506939258001010800001080000506400001520019200382003899960310018800102080000208000020038200381180021109101080000100000502052111613122003580000102003920039200392003920039
80024200381502439258001010800001080000506400001520019200382003899960310018800102080000208000020038200381180021109101080000100000502052121612122003580000102003920039200392003920039
8002420038150939258001010800001080000506400001520019200382003899960310018800102080000208000020038200381180021109101080000100030502052131613112003580000102003920039200392003920039
8002420038150039258001010800001080000506407601520019200382003899960310018800102080000208000020038200381180021109101080000100002502054101612112003580000102003920039200392003920039
80024200871504839258001010800001080000506400000520019200382003899960310018800102080000208000020038200381180021109101080000100000502050121612122003580000102003920039200392003920039
8002420038150039258001010800001080000506400001520019200382003899960310018800102080000208000020038200381180021109101080000100030502054131612112003580000102003920039200392003920086
8002420038150060258001010800001080000506400001020019200382003899960310018800102080000208000020038200381180021109101080000100130502000121613102003580000102003920039200392003920039
8002420038150039258001010800001080193506400000020019200382003899960310018800102080000208000020038200381180021109101080000100030502004121611112003580000102003920039200392003920039