Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

REV64 (vector, 16B)

Test 1: uops

Code:

  rev64 v0.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037151206116862510001000100026452112018203720371571318951000100010002037203711100110000673116111786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715306116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150027216862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100002173116111786100020382038203820382038
1004203715008216862510001000100026452112018203720371571318951000100010002037203711100110000373116111786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000973116111786100020382038203820382038
1004203716906116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037151206116862510001000100026452112018203720371571318951000100010002037203711100110000373116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  rev64 v0.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000001891968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820086
1020420085150000006119686251010010010000100100005002847521120018200372003718421181879710100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000008219686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000710116111979120100001002003820038200382003820038
102042003715000000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010001071011611198240100001002003820038200382003820038
1020420037150000008141968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000000611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010003071011611198570100001002003820038200382003820038
1020420037150000002731968625101001001000010010456500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000000611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000073411611197910100001002003820038200382003820038
10204200371500000014051968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640316221978610000102003820038200382003820038
10024200371502061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
10024200371500061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
10024200371500061196862510010101000010100005028475211200182003720178184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
10024200371500061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
10024200371500061196862510010101000010100005028475211200182003720037184433187671001020100002210000200372003711100211091010100001000640216221978610000102003820038200382003820038
10024200371500061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
10024200371500061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
10024200371500061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
10024200371500061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  rev64 v0.16b, v8.16b
  rev64 v1.16b, v8.16b
  rev64 v2.16b, v8.16b
  rev64 v3.16b, v8.16b
  rev64 v4.16b, v8.16b
  rev64 v5.16b, v8.16b
  rev64 v6.16b, v8.16b
  rev64 v7.16b, v8.16b
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003815000005562580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151182161220035800001002003920039200392003920039
80204200381500000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151182162220035800001002003920039200392003920039
80204200381500000922580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181161220035800001002003920039200392003920039
80204200381500002071172580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151182162220035800001002003920039200392003920039
80204201411500000712580108100800081008002050064168802001920038200389977699898012020080032200800322003820038118020110099100100800001000011151542161220035800001002009020039200392019620039
802042003815000102192580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151182162120035800001002003920039200912003920039
80204200381501100502580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181162220035800001002003920039200392003920039
80204200381500000502580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001001011151181162220035800001002003920039200392003920039
802042003815000001132580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181162220035800001002003920039200892003920090
802042003815000001132580108100800081008002050064013202001920098200389977699898012020080032200800322003820038218020110099100100800001000011151182162220035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005115000000008125800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000000000502009161062003580000102003920039200392003920039
80024200381500000000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000050200101610102003580000102003920039200392003920039
800242003815000000003925800101080000108000050640000120019200382003899963100468001020800002080000200382003811800211091010800001000001000502007168102003580000102003920039200392003920039
800242003815000003008125800101080000108000050640000020019200382003899963100188001020800002080036200382003811800211091010800001000000000502008168102003580000102003920039200392003920039
8002420038150000000070425800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000000060502006168102003580000102003920039200392003920039
800242003815000000008125800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000000000502008168102003580000102003920039200392003920039
80024200381500000000102258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000000005020010161082003580000102003920039200392003920039
8002420038150000000039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000000005020010168102003580000102003920039200392003920039
8002420038150000000066025800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000000000502008168102003580000102003920039200392003920039
80024200381500000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100000000050200111611112003580000102003920039200392003920039