Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

REV64 (vector, 4S)

Test 1: uops

Code:

  rev64 v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371500000000611686251000100010002645211201820372037157131895100010001000203720371110011000000000073116111786100020382038203820382038
100420371500000000611686251000100010002645211201820372037157131895100010001000203720371110011000000000073116111786100020382038203820382038
1004203715000000002511686251000100010002645211201820372037157131895100010001000203720371110011000000003073116111786100020382038203820382038
100420371500000000611686251000100010002645210201820372037157131895100010001000203720371110011000000100073116111786100020382038203820382038
100420371500000000611686251000100010002645210201820372037157131895100010001000203720371110011000000000073116111786100020382038203820382038
100420371500000000841686251000100010002645210201820372037157131895100010001000203720371110011000000000073116111786100020382038203820382038
100420371500000000841686251000100010002645211201820372037157131895100010001000203720371110011000000000073116111786100020382038203820382038
100420371500000000611686251000100010002645210201820372037157131895100010001000203720371110011000000000073116111786100020382038203820382038
100420371500000000611686251000100010002645211201820372037157131895100010001000203720371110011000000300073116111786100020382038203820382038
1004203715000001500611686251000100010002645211201820372037157131895100010001000203720371110011000000006073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  rev64 v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000000061196862510100100100001001000050028475212001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611200340100001002003820038200382003820038
102042003715000000061196862510100100100001001000050028475212001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000000061196862510100100100001001000050028475212001820037200371842131874510100200100002001000020037200371110201100991001001000010000671011611197910100001002003820038200382003820038
1020420037150000000103196862510100100100001001000050028475212001820037200371842131874510100200100002001000020037200371110201100991001001000010000080411611197910100001002003820038200382003820038
102042003715000000061196862510100100100001001000050028475212001820037200371842131874510100200100002001000020037200371110201100991001001000010020071011611197910100001002003820038200382003820038
102042003715000000061196862510100100100001001000050028475212001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000000061196862510100100100001001000050028475212001820037200371842131874510100200100002001000020037200371110201100991001001000010001071011611197910100001002003820038200382003820038
102042003715000000061196862510100100100001001000050028475212001820037201811842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000000061196862510100100100001001000050028475212001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000000061196862510100100100001001000050028475212001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150066196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150082196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372008311100211091010100001000640216221978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001010640216221978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  rev64 v0.4s, v8.4s
  rev64 v1.4s, v8.4s
  rev64 v2.4s, v8.4s
  rev64 v3.4s, v8.4s
  rev64 v4.4s, v8.4s
  rev64 v5.4s, v8.4s
  rev64 v6.4s, v8.4s
  rev64 v7.4s, v8.4s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200601500002925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010001511151180160020035800001002003920039200392003920039
8020420038150000292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
8020420038150000292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
80204200381500003142580392100800081008002050064013202013220038200389977699898012020080032200800322009020038118020110099100100800001000011151180160020035800001002003920039200392003920039
8020420038150000292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
80204200381500002925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010001211151180160020035800001002003920039200392003920039
8020420038150000292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
8020420038150000282225801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010007811151180160020035800001002003920039200392003920039
8020420038150000292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000611151180160020035800001002003920039200392003920039
8020420038150000292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150000000039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000250111005020216222003580000102003920039200392003920039
800242003815000000003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000029075005020116112003580000102003920039200392003920039
80024200381500000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100003200005020116112003580000102003920039200392003920039
800242003815000000002522580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100002500005020116112003580000102003920039200392003920039
800242003815000000003925800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000019078005020116112003580000102003920039200392003920039
8002420038150000000039258001010800001080000506400001200192019020038999671001880010208000020800002003820038118002110910108000010000203005020116112003580000102003920039200392003920039
8002420038150000000039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000480177005020116112003580000102003920039200392003920039
8002420038150000000039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000003005020116112003580000102003920039200392003920039
8002420038150000000039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000103005020116222003580000102003920039200392003920039
8002420038150000000039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000000005020116112003580000102003920039200392003920039