Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

RSUBHN (2D)

Test 1: uops

Code:

  rsubhn v0.2s, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303722061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303723061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303723061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037230330254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037231861254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303722061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303722061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303722061254825100010001000398313301830373037241532895100010002000303730371110011000073124112630100030383038303830383038
1004303723061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303722961254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  rsubhn v0.2s, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003722400000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003722400000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
10204300372250000014682954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
1002430037225006312954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722400822954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830080300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  rsubhn v0.2s, v1.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037224000061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
1020430037224000061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
1020430037224000061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
1020430037224000061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
1020430037225000961295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
10204300372250005761295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000006403162229630010000103003830038302273003830038
10024300372250000061295482510010101000810100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000206402162229630010000103003830038300383008530038
10024300372250000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000006406162229630010000103003830038300383003830038
10024300372250000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001066006402162229630210000103003830038300383003830038
10024300372250000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630310000103003830038300383003830038
10024300372250000061295484410020101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001010006402162229630010000103003830038300383003830038
1002430037225000264082295482510010101000010100005042813841300183003730037282873287671001020100002020000300373003711100211091010100001008228006402162229630010000103003830038300383003830038
1002430037225000005419295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
10024300372240000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
10024300372250000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  rsubhn v0.2s, v8.2d, v9.2d
  rsubhn v1.2s, v8.2d, v9.2d
  rsubhn v2.2s, v8.2d, v9.2d
  rsubhn v3.2s, v8.2d, v9.2d
  rsubhn v4.2s, v8.2d, v9.2d
  rsubhn v5.2s, v8.2d, v9.2d
  rsubhn v6.2s, v8.2d, v9.2d
  rsubhn v7.2s, v8.2d, v9.2d
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03091e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200391500002422580100100800001008000050064000002002020039200399973039997801002008000020016000020039200391180201100991001008000010000780511410167720036800001002004020040200402004020040
8020420039150000242258010010080000100800005006400000200202003920039997303999780100200800002001600002003920039118020110099100100800001000014405114101691020036800001002004020040200402004020040
802052003915000024225801001008000010080000500640000120020200392003999730399978010020080000200160000200392003911802011009910010080000100010051149169920036800001002004020040200402004020040
80204200391500210024225801001008000010080000500640000020020200392003999730399978010020080000200160000200392003911802011009910010080000100000051141016101020036800001002004020040200402004020040
8020420039150000242258010010080000100800005006400000200202003920039997303999780100200800002001600002003920039118020110099100100800001000099051141016101120036800001002004020040200402004020040
802042003915000024225801001008000010080000500640000020020200392003999730399978010020080000200160000200392003911802011009910010080000100009905114916111120036800001002004020040200402004020040
802042003915000024225801001008000010080000500640000020020200392003999730399978010020080000200160000200392003911802011009910010080000100006051149169920036800001002004020040200402004020040
802042003915000024225801001008000010080000500640000020020200392003999730399978010020080000200160000200392003911802011009910010080000100000051149169920036800001002004020040200402004020040
802042003915000024225801001008000010080000500640000020020200392003999730399978010020080000200160000200392003911802011009910010080000100000051149169920036800001002004020040200402004020040
802042003915000024225801001008000010080000500640000020020200392003999730399978010020080000200160000200392003911802011009910010080000100000051149169920036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150040258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000100010550200116112003680000102004020040200402004020040
80024200391500402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050200116112003680000102004020040200402004020040
80024200391500682580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050200116112003680000102004020040200402004020040
80024200391500402580302108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050200116112003680000102004020040200402004020040
80024200391503402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000050200116112003680000102004020040200402004020040
80024200391500402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050200116112003680000102004020040200402004020040
80024200391500402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050200116112003680000102004020040200402004020040
8002420039150040258001010800001080000506400000120020200392003999963100198001020800002016000020039200391180021109101080000100010250200116112003680000102004020040200402004020040
80024200391500402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050200116112003680000102004020040200402004020040
80024200391500402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050200116112003680000102004020040200402004020040