Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

RSUBHN (4S)

Test 1: uops

Code:

  rsubhn v0.4h, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd0d5map dispatch bubble (d6)ddfetch restart (de)dfe0? simd retires (ee)f5f6f7f8fd
10043037220372254825100010001000398313130183037303724153289510001000200030373037111001100007901161132630100030383038303830383038
100430372327061254825100010001000398313130183037303724153289510001000200030373037111001100007901161132630100030383038303830383038
1004303723264061254825100010001000398313130183037303724153289510001000200030373037111001100007901161132630100030383038303830383038
10043037220061254825100010001000398313130183037303724153289510001000200030373037111001100007901161132630100030383038303830383038
10043037220061254825100010001000398313130183037303724153289510001000200030373037111001100007901161132630100030383038303830383038
10043037239061254825100010001000398313130183037303724153289510001000200030373037111001100017901161132630100030383038303830383038
100430372360061254825100010001000398313130183037303724153289510001000200030373037111001100007901161132630100030383038303830383038
10043037230061254825100010001000398313130183037303724153289510001000200030373037111001100007901161132630100030383038303830383038
10043037230061254825100010001000398313130183037303724153289510001000200030373037111001100007901161132630100030383038303830383038
10043037230061254825100010001000398313130183037303724153289510001000200030373037111001100007901161132630100030383038303830383038

Test 2: Latency 1->2

Code:

  rsubhn v0.4h, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430085226106129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001001007101161129634100001003003830038300383003830038
1020430037224006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001001007101161129670100001003003830038300383003830038
102043003722501626129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001001007101161129634100001003003830038300383003830038
1020430037224006129548251010010010000100100005004277313300183003730037282653287451010020010000204200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313300183003730037282653287451010020010167200200003003730037111020110099100100100001000007321161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250025129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101171129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372240000006129548251001010100001010000504277313300180300373003728287032876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500004206129548251001010100001010000504277313300180300373003728287032876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313300180300373003728304032876710010201000020200003003730037111002110910101000010000000006402242229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313300180300373003728287032876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372240000006129548251001010100001010000504277313300180300373003728287032876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313300180300373003728287032876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313300180300373003728287032876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500002106129548251001910100001010000504277313300180300373003728306032876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372240000006129548251001010100001010000504277313300180300373003728287032876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372240000006129548251001010100001010000504277313300180300373003728287032876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  rsubhn v0.4h, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372254561295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
1020430037224066295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
1020430037224061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372252461295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010007321161129707100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
1020430037224061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
1020430037224061295482510100100100001001000050042773133001830037300372826932874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300842252761295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372240612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006612162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101014850427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  rsubhn v0.4h, v8.4s, v9.4s
  rsubhn v1.4h, v8.4s, v9.4s
  rsubhn v2.4h, v8.4s, v9.4s
  rsubhn v3.4h, v8.4s, v9.4s
  rsubhn v4.4h, v8.4s, v9.4s
  rsubhn v5.4h, v8.4s, v9.4s
  rsubhn v6.4h, v8.4s, v9.4s
  rsubhn v7.4h, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581500041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051102161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
80204200391501041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
802042003915002141258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150001020258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
802042003915000706258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000251101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915010402580010108000010800005064000001200202003920039999603100198001020800002016000020039200391180021109101080000100502071688200360080000102004020040200402004020040
800242003915000402580010108000010800005064000010200202003920039999603100198001020800002016000020039200391180021109101080000100502071688200360080000102004020040200402004020040
8002420039150002302580010108000010800005064000040200202003920039999603100198001020800002016000020039200391180021109101080000100502061665200360080000102011220040200402004020040
800242003915000402580010108000010800005064000041200202003920039999603100198001020800002016000020039200391180021109101080000100502081688200360080000102004020040200402004020040
800242003915000402580010108000010800005064000041200202003920039999603100198001020800002016000020039200391180021109101080000100502071657200360080000102004020040200402004020040
800242003915000402580010108000010800005064000041200202003920039999603100198001020800002016000020039200391180021109101080000100502061677200360080000102004020040200402004020040
800242003915000402580010108000010800005064000040200202003920039999603100198001020800002016000020039200391180021109101080000100502081667200360080000102004020040200402004020040
800242003915000402580010108000010800005064000041200202003920039999603100198001020800002016000020039200391180021109101080000100502061685200360080000102004020101200402004020040
800242003915000402580010108000010800005064000041200202003920039999603100198001020800002016000020039200391180021109101080000100502081677200360080000102004020040200402004020040
800242003915000402580010108000010800005064000051200202003920039999603100198001020800002016000020039200391180021109101080000100502081666200360080000102004020040200402004020040