Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

RSUBHN (8H)

Test 1: uops

Code:

  rsubhn v0.8b, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303724061254825100010001000398313130183037303724153289510001000200030373037111001100000073216112630100030383038303830383038
1004303724361254825100010001000398313130183037303724153289510001000200030373037111001100000373116112630100030383038303830383038
10043037231561254825100010001000398313130183037303724153289510001000200030373037111001100001073116112630100030383038303830383038
1004303723961254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303725061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303722061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303722061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303722061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  rsubhn v0.8b, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l1i tlb fill (04)09181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722410000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000000710116112963425100001003003830038300383003830038
1020430037225000001137295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372250000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000171011611296340100001003003830038300383003830038
1020430037225000331681983295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372250000061295482510100100100001001000065842773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722500012061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000200071011611296340100001003003830085300383003830038
10204300372250000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372250000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722400000103295482510100100100001001000062642773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372240000061295484110100100100001001000050042773130300183003730074282653287451010020010000200200003003730037111020110099100100100001000000071011612296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250004632954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830085
10024300372250007262954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313300183003730037282872028767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  rsubhn v0.8b, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)033a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037224012429548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225042529548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830086
1020430037225064329548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225041029548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225052729548251010010010000100100005004277313130018300373003728265328765101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225049329548251010010010000100100005504277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003008630086300383003830088
10204300372250455529548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100002030071011611296340100001003003830038300383003830038
1020430037225062929548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225052929548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000006129548251001010100001210000504277313030018300853003728287032876710159201000020200003008530037111002110910101000010000000008537976729918410000103051030510305493022730515
1002430511228304101452792649229485163100711410056151104381428681203027030415303692830903728900112062610980222229030368303678110021109101010000100020219585407915735629880310000103037030369303673040730182
10024303682270176936264205529494204100701110040151104370428681203030630357304142831201228910110562011147202230030369303688110021109101010000102221022118006404164529630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287032876710010201000020200003022430037111002110910101000010000000006615165429630010000103003830038300383003830038
100243003722500001206129548441001010100001010000504277313030054300853013228287032879810010201000020200003003730037111002110910101000010000003006404165429630010000103003830086300853003830085
10024300372250000006129548251001010100001010000504277313130018300373003728287032876710010201000020200003003730037111002110910101000010000000006405165429630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287032876710010201000020200003003730037111002110910101000010000000006405165529630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000000006405165429630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287032876710010201000020206583003730037111002110910101000010000100006404164529630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287032876710010201000020200003007330037211002110910101000010022100006405164529630010000103003830038300853008630133

Test 4: throughput

Count: 8

Code:

  rsubhn v0.8b, v8.8h, v9.8h
  rsubhn v1.8b, v8.8h, v9.8h
  rsubhn v2.8b, v8.8h, v9.8h
  rsubhn v3.8b, v8.8h, v9.8h
  rsubhn v4.8b, v8.8h, v9.8h
  rsubhn v5.8b, v8.8h, v9.8h
  rsubhn v6.8b, v8.8h, v9.8h
  rsubhn v7.8b, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420069151061258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001003511021611200360800001002004020040200402004020040
8020420039150041258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000511011612200360800001002004020040200402004020040
802042003915001008258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000511011611200360800001002004020040200402004020040
8020420039150041258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000511011612200360800001002004020040200402004020040
80204200391500231258010010080000100800005006400001200200200392003999733999780100200800002001600002003920093118020110099100100800001000511011611200360800001002004020040200402004020040
8020420039150041258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000511011611200360800001002004020040200402004020040
80204200391500224258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000511011611200360800001002004020040200402004020040
8020420039150041258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000511011611200360800001002004020040200402004020040
8020420039150041258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000511011611200360800001002004020040200402004020040
8020420039150041258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000511011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391500000004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000050201161120036080000102004020040200402004020040
80024200391500000004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000050201161120036080000102004020040200402004020040
80024200391500000004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000050201161120036080000102004020040200402004020040
80024200391500000004025800101080000108000050640000120020200392003999963100198001020800002016000020089200391180021109101080000100000050201161120036080000102004020040200402004020040
80024200391500000004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000050201161120036080000102004020040200402004020040
80024200391500000004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000050201161120036080000102004020040200402004020040
80024200391500100004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000050201161120036080000102004020040200402004020040
80024200391500000004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000050201161120036080000102004020040200402004020040
80024200391500000004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000050201161120036080000102004020040200402004020040
80024200391500000004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000050201161120036080000102004020040200402004020040