Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SABAL2 (vector, 2D)

Test 1: uops

Code:

  sabal2 v0.2d, v1.4s, v2.4s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)dfe0? simd retires (ee)f5f6f7f8fd
10043037220372254825100010001000398313030183037303724153289510001000300030373037111001100000791161132630100030383038303830383038
10043037230061254825100010001000398313030183037303724153289510001000300030373037111001100000791161132630100030383038303830383038
10043037220061254825100010001000398313030183037303724153289510001162300030373037111001100000791161132630100030383038303830383038
10043037220061254825100010001000398313130183037303724153289510001000300030373037111001100000791161132630100030383038303830383038
10043037220061254825100010001000398313130183037303724153289510001000300030373037111001100000791161132630100030383038303830383038
10043037230061254825100010001000398313130183037303724153289510001000300030373037111001100000791161132630100030383038303830383038
100430372300156254825100010081000398313030183037303724153289510001000300030373037111001100010791161132630100030383038303830383038
10043037220061254825100010001000398313030183037303724153289510001000300030373037111001100000791161132630100030383038303830383038
100430372312084254825100010001000398313030183037303724153289510001000300030373037111001100000791161132630100030383038303830383038
10043037230061254825100010001000398313030183037303724153289510001000300030373037111001100030791161132630100030383038303830383038

Test 2: Latency 1->1

Code:

  sabal2 v0.2d, v1.4s, v2.4s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500061295482510100100100001001000050042773130300180300373003728265328745101002001000020030000300373003711102011009910010010000100071213163329634100001003008630038300383003830038
102043017922600061295482510100100100001001000050042773130300180300373003728265328745101002001000020030000300373003711102011009910010010000100071013163329634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773130300180300373003728265328745101002001000020030000300373003711102011009910010010000100071013163329634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773131300180300373003728265328745101002001000020030000300373003711102011009910010010000100371014163329634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773131300180300373003728265328745101002001000020030000300373003711102011009910010010000100071013163329634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773130300180300373003728265328745101002001000020030000300373003711102011009910010010000100071013163329634100001003003830038300383003830038
102043003722509061295482510100100100001001000050042773130300180300373003728265328745101002001000020030000300373003711102011009910010010000100071013163329634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773130300180300373003728265328745101002001000020030000300373003711102011009910010010000100071013163329634100001003003830038300623003830038
1020430037225000103295482510100100100001001000050042773130300180300373003728265328745101002001000020030000300373003711102011009910010010000100071013163329634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773130300180300373003728265328745101002001000020030000300373003711102011009910010010000100071013164329634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010006403163329630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010006403163329630010000103003830038300383003830038
100243003722515612954825100101010000101000050427731303001830037300842828732876710010201000020300003003730037111002110910101000010006402163329630010000103003830038300383003830038
1002430037225061295302510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001001506403163329630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010006402163429630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010006403163329630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010006403163329630010000103003830038300383003830038
10024300372240612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010006403163329630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010006404243229630010000103003830038300383003830038
100243003722506312954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010006402163329630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  sabal2 v0.2d, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500061295482510100100100001001000050042773133001830037300372826532874510100200100002003000030037300371110201100991001001000010002007102162229634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773133001830037300372826532874510100200100002003000030037300371110201100991001001000010000007102162229634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773133001830037300372826532874510100200100002003000030037300371110201100991001001000010003007102162229634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773133001830037300372826532874510100200100002003000030037300371110201100991001001000010001007102162229634100001003003830038300383003830038
1020430037225000726295482510100100100001001000050042773133001830037300372826532874510100200100002003000030037300371110201100991001001000010000007102162229634100001003003830038300383003830038
1020430037224000156295482510100100100001001000050042773133001830037300372826532874510100200100002003000030037300371110201100991001001000010000007102162229634100001003003830038300383003830038
1020430037224051061295482510100100100001001000050042773133001830037300372826532874510100200100002003000030037300371110201100991001001000010000007102162229634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773133001830037300372826532874510100200100002003000030037300371110201100991001001000010000007102162229634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773133001830037300372826532874510100200100002003000030037300371110201100991001001000010021037102162229634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773133001830037300372826532874510100200100002003000030037300371110201100991001001000010000007102162229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500612954825100101010000101000050427731313001830037300372828703287671001020100002030000300373003711100211091010100001000306640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372240061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100010640216222963010000103003830038300383003830038
10024300372251061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830080
10024300372250061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100010640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282877328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250061295482510010111000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000102010640216222963010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  sabal2 v0.2d, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l1i tlb fill (04)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722510612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722400612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000596427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037224091052954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722506129548251001010100001010000504277313030018030037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722406129548251001010100001010000504277313030018030037300372828732876710010201000020300003003730037111002110910101000010410640216222963010000103003830038300383003830038
100243003722516129548251001010100001010000504277313030018030037300372828732876710010201000020300003003730037111002110910101000010020640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313030018030037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313030018030037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313030018030037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313030018030037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722406129548251001010100001010000504277313030018030037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313030018030037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313030018030037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sabal2 v0.2d, v8.4s, v9.4s
  movi v1.16b, 0
  sabal2 v1.2d, v8.4s, v9.4s
  movi v2.16b, 0
  sabal2 v2.2d, v8.4s, v9.4s
  movi v3.16b, 0
  sabal2 v3.2d, v8.4s, v9.4s
  movi v4.16b, 0
  sabal2 v4.2d, v8.4s, v9.4s
  movi v5.16b, 0
  sabal2 v5.2d, v8.4s, v9.4s
  movi v6.16b, 0
  sabal2 v6.2d, v8.4s, v9.4s
  movi v7.16b, 0
  sabal2 v7.2d, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)91inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042008915000812580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100990100100160000100000003001011151611200611600001002006520226202232006520065
1602042006415000392580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100990100100160000100000000001011111611200611600001002006520065200652006520065
1602042006415000392580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100990100100160000100400006001011111611200611600001002006520065200652006520065
1602042006415000392580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100990100100160000100000000001011111611200611600001002006520065200652006520065
1602042006415000392580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100990100100160000100000000001011111611200611600001002006520065200652006520065
1602042006415000812580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100990100100160000100000000001011111611200611600001002006520065200652006520065
1602042006415000392580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100990100100160000100000000001011111611200611600001002006520065200652006520065
1602042006415000392580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100990100100160000100000000001011111611200611600001002006520065200652006520065
1602042006415000392580100100800001008000050064000012004520064200643228010020080000200240408200642006411160201100990100100160000100000000011011111611200611600001002006520065200652006520065
1602042006415000392580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100990100100160000100000000001011111611200611600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6erob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200881500004527800121280000128000062640000110200322005120051032280012208000020240000200512005111160021109101016000010001004282120252111313200482201160000102005220052200522005220052
160024200511500004527800121280000128000062640000115200322005120051032280012208000020240000200512005111160021109101016000010001003482113342121312200482201160000102005220052200522005220052
160024200511500004566800121280000128000062640000115200322005120051032280012208000020240000200512005111160021109101016000010001003182112252111310200482201160000102005220052200522005220052
16002420051150000452780012128000012800006264000011520032200512005103228001220800002024000020053200511116002110910101600001000100318211634211159200482201160000102006120052200522005220052
160024200511500004527800121280000128000062640000115200322005120051032280012208000020240000200532005111160021109101016000010001003682111342111013200482201160000102005220052200522005220052
16002420051150000452780012128000012800006264000011520032200512005103228001220800002024000020051200511116002110910101600001000100358311425211129200482201160000102005220052200522005220052
1600242005115000015427800121280000128000062640000115200322006020051032280012208000020240000200512005111160021109101016000010001003982115252111013200482201160000102005220052200522005220052
1600242005115000012927800121280000128000062640000115200322005120051032280012208000020240000200512005111160021109101016000010001003282113342111310200482201160000102005220052200522005220052
160024200511500004527800121280000128000062640000115200322005120051032280012208000020240000200512005111160021109101016000010001003382110252111413200482201160000102005220052200522005220052
160024200511500004527800121280000128000062640000115200322005120051032280012208000020240000200512005111160021109101016000010001003682111252111414200482201160000102005220052200522005220052

Test 6: throughput

Count: 16

Code:

  sabal2 v0.2d, v16.4s, v17.4s
  sabal2 v1.2d, v16.4s, v17.4s
  sabal2 v2.2d, v16.4s, v17.4s
  sabal2 v3.2d, v16.4s, v17.4s
  sabal2 v4.2d, v16.4s, v17.4s
  sabal2 v5.2d, v16.4s, v17.4s
  sabal2 v6.2d, v16.4s, v17.4s
  sabal2 v7.2d, v16.4s, v17.4s
  sabal2 v8.2d, v16.4s, v17.4s
  sabal2 v9.2d, v16.4s, v17.4s
  sabal2 v10.2d, v16.4s, v17.4s
  sabal2 v11.2d, v16.4s, v17.4s
  sabal2 v12.2d, v16.4s, v17.4s
  sabal2 v13.2d, v16.4s, v17.4s
  sabal2 v14.2d, v16.4s, v17.4s
  sabal2 v15.2d, v16.4s, v17.4s
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)031e373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204400603000175002516011710016000110016000050012800004002004003940040199733199981601002001600002004800004004840039111602011009910010016000010001011051611400451600001004004040053400504004940040
160204400493000614202516011710016000010016000050012800004002004004040039199733200071601002001600002004800004003940039111602011009910010016000010001011021611400361600001004005040040400724004140049
16020440052300304102516011710016000010016000050012800004005204004840039199733199971601002001600002004800004004840048111602011009910010016000010001011021611400861600001004004040072400494004040040
16020440039300014102516010010016001710016000050023990554002004003940039199733199971601002001600002004800004004040049111602011009910010016000010001011021611400461600001004005040050400494004940049
16020440039300004102516010010016000110016000050012800004002004003940039199733200061601002001600002004800004004840049111602011009910010016000010001011021611400461600001004004040040400504005040050
16020440048300015102516010010016000010016000050023990554002004004840039199733199971601002001600002004800004004940048111602011009910010016000010001011021611400451600001004004940040400494004940040
1602044003929901723302516010010016001710016000050023989994002004004840039199733199971601002001600002004800004003940040111602011009910010016000010001011021611400491600001004004040041400404005040041
160204400393000175102516016110016000010016000050012800004002004004940039199733199971601002001600002004800004004840039111602011009910010016000010001011021611400461600001004004040050400404004040040
160204400483000614102516011710016000010016000050012800004003004003940071199733199971601002001600002004800004005240040111602011009910010016000010001011021611400361600001004004040040400504005040050
16020440048300004102516011710016000010016000050012800004002004003940049199733200061601002001600002004800004003940048111602011009910010016000010001012721611400461600001004004940040400504004040050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03l1i tlb fill (04)1e1f373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002440048300000177110251600101016000010160000501280000114002040039400391999632002916001020160000204800004003940039111600211091010160000100001002234145162111627400360206160000104004040040400404004040040
160024401623000001460251600281016001710160000501280000114002040039400711999632001916001020160000204800004004940039111600211091010160000100001010938128162111620400360206160000104004040040400404007240040
160024400393000000460251600271016001710160000502438865114002040039400481999632001916001020160000204800004003940039111600211091010160000100031002234120162111620400360206160000104004040040400404007240040
160024400393000000460251600101016000010160000502398999114002040049400391999632001916001020160000204800004003940039111600211091010160000100001002234125162111520400360206160000104004040040400724004040072
160024400393000000460251600101016000010160000501280000114002040039400391999672002816001020160000204806364009140048111600211091010160000104101002234120162112115400450206160000104004040040400404004040049
1600244003930000002440251600271016001710160000501280000114003040039400491999632001916001020160000204800004003940280111600211091010160000100001002234120162111525400360206160000104004940040400504005040040
1600244003930000007470251600101016000010160000501280000114002040039400391999632001916001020160000204800004003940048111600211091010160000100001002235117162111915400360206160000104004040040400724004040040
160024400393000000460251600101016000010160000501319997114002040039400391999632001916001020160000204800004004840039111600211091010160000100001002235116162111915400360206160000104004040040400724004040040
160024400393000001550251600711016000010160000502398999114002040039400391999632002816001020160000204800004003940039111600211091010160000100001002234122162112520400360206160000104004040040400404004040049
160024400393000000460251600101016000010160000501280000114002040039400712000232005116001020160000204800004004840039111600211091010160000100001002234123162111519400460207160000104005040050400404004940040