Firestorm: SABAL (vector, 2D) measurements

Code:

  sabal v0.2d, v1.2s, v2.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3085	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	6	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	19	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	75	61	2548	44	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	24	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	1	0	12	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  sabal v0.2d, v1.2s, v2.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	124	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	712	0	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	84	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	2	16	2	3	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	84	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	84	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	3	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	523	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	214	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	124	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	177	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	1	105	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	1	84	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	224	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	107	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	3272	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1389	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	2	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	126	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	350	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10025	30037	225	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	5915	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	26	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	2	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	520	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  sabal v0.2d, v0.2s, v1.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	6	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28786	10159	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	6	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	226	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	1	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29539	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->3

Code:

  sabal v0.2d, v1.2s, v0.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	82	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30086	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	224	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sabal v0.2d, v8.2s, v9.2s
  movi v1.16b, 0
  sabal v1.2d, v8.2s, v9.2s
  movi v2.16b, 0
  sabal v2.2d, v8.2s, v9.2s
  movi v3.16b, 0
  sabal v3.2d, v8.2s, v9.2s
  movi v4.16b, 0
  sabal v4.2d, v8.2s, v9.2s
  movi v5.16b, 0
  sabal v5.2d, v8.2s, v9.2s
  movi v6.16b, 0
  sabal v6.2d, v8.2s, v9.2s
  movi v7.16b, 0
  sabal v7.2d, v8.2s, v9.2s

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20103	151	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10114	5	16	4	4	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	32636	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	1	0	0	10114	3	16	3	5	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10115	5	16	5	5	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	60	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10114	5	16	5	5	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	123	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10113	3	16	4	5	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10115	4	16	5	4	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10114	4	16	5	5	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10114	5	16	4	4	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	81	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10114	4	16	4	4	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10113	4	16	4	4	20061	0	160000	100	20065	20065	20065	20065	20065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20059	150	0	45	27	80012	12	80000	12	80000	62	640000	1	1	10	20032	20051	20051	0	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	9	10029	13	3	1	14	25	2	1	1	10	6	20048	2	20	0	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	51	27	80012	12	80000	12	80000	62	640000	1	1	10	20041	20051	20060	0	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10029	16	6	1	6	34	4	1	1	6	10	20057	2	40	0	2	160000	10	20061	20061	20052	20061	20052
160024	20060	150	285	51	29	80012	12	80000	12	80000	62	640000	1	1	10	20032	20060	20060	0	3	84	80012	20	80210	20	240000	20060	20055	1	1	160021	10	9	10	10	160000	10	0	1	0	3	10033	13	6	1	10	25	2	1	1	6	10	20048	2	20	0	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	45	27	80012	12	80000	12	80000	62	640000	1	1	10	20032	20051	20051	0	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10033	13	6	1	10	25	2	1	1	10	6	20048	2	20	0	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	45	27	80012	12	80000	12	80000	62	640000	1	1	10	20032	20051	20051	0	3	22	80012	20	80000	20	240000	20051	20051	2	1	160021	10	9	10	10	160000	10	0	0	0	0	10033	13	6	1	10	25	2	1	1	11	6	20048	2	20	0	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	45	27	80012	12	80000	12	80000	62	640000	1	1	10	20032	20051	20051	0	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10029	13	6	1	6	25	2	1	1	10	6	20048	2	20	0	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	315	45	27	80012	12	80000	12	80000	62	640000	1	1	10	20032	20051	20051	0	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10029	13	6	1	10	25	2	1	1	6	10	20048	2	20	0	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	366	45	27	80012	12	80000	12	80000	62	640000	1	1	10	20032	20051	20051	5	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10033	13	6	1	10	25	2	1	1	6	10	20048	2	20	0	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	45	27	80012	12	80000	12	80000	62	640000	1	1	10	20032	20051	20051	0	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	2	0	0	0	10033	13	6	1	7	25	2	1	1	6	10	20048	2	20	0	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	45	27	80012	12	80000	12	80000	62	640000	1	1	10	20032	20051	20051	0	3	42	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10033	13	7	1	10	25	2	1	1	10	6	20048	2	20	0	1	160000	10	20052	20052	20052	20052	20052

Test 6: throughput

Count: 16

Code:

  sabal v0.2d, v16.2s, v17.2s
  sabal v1.2d, v16.2s, v17.2s
  sabal v2.2d, v16.2s, v17.2s
  sabal v3.2d, v16.2s, v17.2s
  sabal v4.2d, v16.2s, v17.2s
  sabal v5.2d, v16.2s, v17.2s
  sabal v6.2d, v16.2s, v17.2s
  sabal v7.2d, v16.2s, v17.2s
  sabal v8.2d, v16.2s, v17.2s
  sabal v9.2d, v16.2s, v17.2s
  sabal v10.2d, v16.2s, v17.2s
  sabal v11.2d, v16.2s, v17.2s
  sabal v12.2d, v16.2s, v17.2s
  sabal v13.2d, v16.2s, v17.2s
  sabal v14.2d, v16.2s, v17.2s
  sabal v15.2d, v16.2s, v17.2s

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	37	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40060	300	0	162	0	0	41	25	160118	100	160000	100	160000	500	2438865	1	40121	40039	40039	19973	3	20007	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40046	160000	100	40049	40040	40040	40040	40040
160204	40039	299	0	246	0	18	41	25	160118	100	160000	100	160000	500	2438865	1	40020	40039	40048	19973	3	19997	160100	200	160000	200	480000	40049	40049	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40036	160000	100	40040	40040	40050	40040	40050
160204	40039	300	0	129	0	18	41	25	160100	100	160000	100	160000	500	1280000	1	40020	40049	40039	19973	3	19997	160100	200	160000	200	480000	40048	40049	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40046	160000	100	40040	40040	40041	40052	40050
160204	40039	300	0	27	0	17	41	25	160100	100	160000	100	160000	500	2398999	1	40030	40039	40039	19973	3	20007	160100	200	160000	200	480000	40039	40049	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40046	160000	100	40040	40050	40040	40040	40040
160204	40039	300	0	123	0	0	41	25	160100	100	160000	100	160000	500	1280000	1	40020	40039	40039	19980	3	19997	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	299	0	78	0	0	41	25	160100	100	160000	100	160000	500	2438865	1	40020	40048	40039	19973	3	20007	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40036	160000	100	40040	40050	40040	40040	40040
160204	40049	299	0	90	0	0	41	25	160100	100	160000	100	160000	500	2398999	1	40030	40039	40039	19973	26	20007	160100	200	160000	200	480000	40049	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40036	160000	100	40040	40050	40040	40040	40040
160204	40049	299	0	81	0	0	41	25	160100	100	160000	100	160000	500	1280000	1	40020	40049	40049	19973	3	19997	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40046	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	117	0	18	41	25	160100	100	160000	100	160000	500	2438865	1	40021	40039	40039	19973	3	19997	160100	200	160000	200	480000	40039	40049	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40036	160000	100	40050	40040	40040	40040	40040
160204	40049	300	0	123	0	18	51	25	160100	100	160000	100	160000	500	2438865	1	40020	40049	40039	19973	3	19997	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40046	160000	100	40040	40040	40040	40050	40050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40049	300	0	0	0	0	0	72	0	0	47	0	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	40040	40049	19996	3	20019	160010	20	160000	20	480000	40040	40049	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	13	6	2	4	16	2	1	2	4	5	40036	0	40	18	0	160000	10	40041	40049	40049	40049	40049
160024	40048	300	0	0	0	0	0	18	0	17	718	0	25	160010	10	160000	10	160000	50	1280000	0	1	10	40029	40048	40048	20013	3	20020	160010	20	160000	20	480000	40039	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	3	0	0	10024	16	5	2	4	16	4	2	1	3	4	40045	0	40	9	0	160000	10	40049	40050	40040	40049	40041
160024	40039	299	0	0	0	0	0	246	0	0	61	0	25	160010	10	160000	10	160000	50	1280000	0	1	10	40029	40039	40039	19996	3	20019	160010	20	160000	20	480000	40049	40048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	16	5	2	4	16	4	2	2	4	4	40046	0	40	18	0	160000	10	40040	40049	40040	40040	40040
160024	40039	300	0	0	0	0	0	330	0	17	46	0	25	160027	10	160000	10	160000	50	1280000	0	1	10	40020	40049	40048	19996	3	20019	160010	20	160000	20	480000	40039	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10024	16	6	2	3	16	4	2	2	4	4	40036	0	40	6	0	160000	10	40041	40049	40049	40040	40040
160024	40039	300	0	0	0	0	0	279	0	17	934	0	25	160010	10	160017	10	160000	50	1280000	0	1	10	40020	40039	40049	19996	3	20029	160010	20	160000	20	480000	40048	40049	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10024	16	5	2	4	16	4	2	2	4	4	40046	0	20	18	0	160000	10	40040	40040	40040	40049	40040
160024	40039	300	0	0	0	0	0	111	0	0	52	0	25	160027	10	160017	10	160000	50	2398999	1	1	10	40029	40039	40039	19996	3	20019	160010	20	160000	20	482985	40546	40600	10	1	160021	10	9	10	10	160000	10	0	2	0	0	0	0	4765	10219	16	8	2	5	132	4	2	1	4	4	40472	2	40	13	0	160000	10	40671	40560	40678	40694	40358
160024	40632	304	0	0	0	8	10	1191	792	157	1945	26	202	161333	12	161253	11	161451	60	2284964	0	1	10	40582	40607	40640	20125	46	20346	161293	20	161471	20	484089	40629	40746	11	1	160021	10	9	10	10	160000	10	0	3	3	1	1	2	5810	10211	16	7	2	3	140	4	2	1	5	8	40554	2	40	18	0	160000	10	40697	40750	40662	40583	40704
160024	40708	305	1	0	1	10	10	1323	968	0	55	0	25	160027	10	160017	10	160000	50	2438865	0	1	10	40029	40048	40039	19996	3	20028	160010	20	160000	20	480000	40048	40048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10024	16	7	2	4	16	4	2	1	4	4	40036	0	20	6	0	160000	10	40040	40049	40040	40040	40041
160024	40039	300	0	0	0	0	0	48	0	0	717	0	25	160010	10	160000	10	160000	50	2398999	0	1	10	40029	40039	40048	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10024	16	6	2	3	16	2	1	2	3	4	40045	0	40	12	0	160000	10	40040	40049	40040	40049	40040
160024	40039	300	0	0	0	0	0	99	0	0	61	0	25	160010	10	160000	10	160000	50	1280000	0	1	10	40020	40039	40039	19996	3	20028	160010	20	160000	20	480000	40048	40039	2	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10024	16	7	2	4	16	4	2	2	3	4	40045	0	40	18	0	160000	10	40049	40049	40049	40049	40049

SABAL (vector, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations