Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SABA (vector, 8B)

Test 1: uops

Code:

  saba v0.8b, v1.8b, v2.8b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230612548251000100010003983131301830373037241532895100010003000303730371110011000973116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100030003037303711100110001573116112630100030383038303830383038
10043037230612548251000100010003983130301830373037241532895100010003000303730371110011000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100030003037303711100110003073116112630100030383038303830383038
10043037230612548251000100010003983130301830373037241532895100010003000303730371110011000073116112630100030383038303830383038
100430372236125482510001000100039831303018303730372415328951000100030003037303711100110002773116112630100030383038303830383038
10043037220612548251000100010003983131301830373037241532895100010003000303730371110011000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100030003037303711100110001873116112630100030383038303830383038
10043037230612548251000100010003983130301830373037241532895100010003000303730371110011000073116112630100030383038303830383038
100430372301032548251000100010003983130301830373037241532895100010003000303730371110011000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  saba v0.8b, v1.8b, v2.8b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09181e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000006129548251010010010000100100005004277313130018300373003728265032874510100200100002003000030037300371110201100991001001000010000071002162229634100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313130018300373003728265032874510100200100002003000030037300371110201100991001001000010000071002162229634100001003003830038300383003830038
10204300372250100006129548251010010010000100100005004277313030054300373003728265032874510100200100002003000030037300371110201100991001001000010000071002162229634100001003003830038300383003830038
10204300372250000006129548251010011610000100100005004277313030018300373003728265032874510100200100002003000030037300371110201100991001001000010003071012162229634100001003003830038300383003830038
10204300372240000006129548251010010010000100100005004277313030018300373003728265032874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313030018300373003728265032874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
102043003722500000010329548251010010010000100100005004277313030018300373003728265032874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
10204300372250100006129548251010010010000100100005004277313030018300373003728265032874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313030018300373003728265032874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313030018300373003728265032874510100200100002003000030037300371110201100991001001000010000071012163229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000066402162229630010000103003830086300383003830038
1002430037225000000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
100243003722500000135006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  saba v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250612954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372240612954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
1020430037225013362954825101001001000010010000500427731313001830037300372826503287451010020010000200300003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
1020430037225013982954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826503287451010020010000200300003003730037111020110099100100100001000071021611296340100001003003830038300383003830038
1020430037225019012954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l1i tlb fill (04)1e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500021522954825100101010000101000050427731330018030037300372828732876710010201000020300003003730037111002110910101000010000644111611102963010000103003830038300383003830038
100243003722500021942954825100101010000101000050427731330018030037300372828732876710010201000020300003003730037111002110910101000010000644101611112963010000103003830038300383003830038
10024300372250002622954825100101010000101000050427731330018030037300372828732876710010201000020300003003730037111002110910101000010000644111610112963010000103003830038300383003830038
100243003722500021922954825100101010000101000050427731330018030037300372828732876710010201000020300003003730037111002110910101000010000644111611102963010000103003830038300383003830038
10024300372240002622954825100101010000101000050427731330018030037300372828732876710010201000020300003003730037111002110910101000010000644111611112963010000103003830038300383003830038
100243003722500021922954825100101010000101000050427731330065030037300372828732876710010201000020300003003730037111002110910101000010000644111611102963010000103003830038300383003830038
100243003722500029762954825100101010000101000050427731330018030037300372828732876710010201000020300003003730037111002110910101000010000644111611112963010000103003830038300383003830038
100243003722500021672954825100101010000101000050427731330018030037300372828732876710010201000020300003003730037111002110910101000010000644101611112963010000103003830038300383003830038
10024300372250002622954825100101010000101000050427731330018030037300372828732876710010201000020300003003730037111002110910101000010000644101610112963010000103003830038300383003830038
10024300372250002622954825100101010000101000050427731330018030037300372828732876710010201000020300003003730037111002110910101000010000644111610112963010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  saba v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fa9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225612954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000007102161129634100001003003830038300383003830038
10204300372257262954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000007101164129634100001003003830038300383003830038
1020430037225612954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225612954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225612954825101001001000010010000500427731303001803003730037282653287451010020010000200300003008430037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372253462954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372252512954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000307101161129634100001003003830038300383003830038
1020430037225612954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372256129548251010010010000100100005004277313030018030037300372826525287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225612954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225021612954844100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722509612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722509612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002210910101000010000640216222963010000103003830038300383003830083
1002430037225006129548251001010100001010000504277313030018300373003728287262876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722400612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010100640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222969910000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  saba v0.8b, v8.8b, v9.8b
  movi v1.16b, 0
  saba v1.8b, v8.8b, v9.8b
  movi v2.16b, 0
  saba v2.8b, v8.8b, v9.8b
  movi v3.16b, 0
  saba v3.8b, v8.8b, v9.8b
  movi v4.16b, 0
  saba v4.8b, v8.8b, v9.8b
  movi v5.16b, 0
  saba v5.8b, v8.8b, v9.8b
  movi v6.16b, 0
  saba v6.8b, v8.8b, v9.8b
  movi v7.16b, 0
  saba v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020420065150153925801001008000010080000500640000020045200642006432280100200800002002400002006420064111602011009910010016000010001011331645200611600001002006520065200652006520065
1602042006415103925801001008000010080000500640000020045200642006432280100200800002002400002006420064111602011009910010016000010001011541655200611600001002006520065200652006520065
1602042006415003925801001008000010080000500640000020045200642006432280100200800002002400002006420064111602011009910010016000010001011551654200611600001002006520065200652006520065
1602042006415003925801001008000010080000500640000020045200642006432280100200800002002400002006420064111602011009910010016000010001011451635200611600001002006520065200652006520065
16020420064150039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100010114414944200611600001002006520065200652006520065
1602042006415003925801001008000010080000500640000020121200642006432280100200800002002400002006420064111602011009910010016000010021011341644200611600001002006520065200652006520065
1602042006415003925801001008000010080000500640000120045200642006432280100200800002002400002006420064111602011009910010016000010001011441644200611600001002013420065200652006520065
1602042006415003925801001008000010080000500640000120045200642006432280100200800002002400002006420064111602011009910010016000010001011441643200611600001002006520065200652006520065
1602042006415003925801001008000010080000500640000120045200642006432280100200800002002400002006420064111602011009910010016000010001011451654200611600001002006520065200652006520065
1602042006415103925801001008000010080000500640000120045200642006432280100200800002002400002006420064111602011009910010016000010001011541653200611600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fbranch cond mispred nonspec (c5)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200881501444527800121280000128000062640000112003220051200513228001220800002024000020051200511116002110910101600001001003131122252111818200482201160000102005220052200522005220052
160024200511500452780012128000012801046264083211200322005120051322800122080000202400002005120051111600211091010160000100100413111725211177200482201160000102006120052200522005220052
1600242005115105202780012128000012800006264000011200322005120051322800122080000202400002005120051111600211091010160000100100413111725211188200482201160000102005220052200522005220052
1600242005115030452780012128000012800006264000011200322005120051322800122080000202400002005120051111600211091010160000101100413111725412717200572402160000102006120061200612013120061
1600242006015018452780012128000012800006264000011200322005120051322800122080000202400002005120051111600211091010160000100100413111725211158200482201160000102005220052200522005220052
1600242005115023145278001212800001280000626400001120032200512005132280012208000020240000200512005111160021109101016000010010034622725212818200482201160000102005220052200522005220052
16002420051150129452980012128000012800006264000011200322005120051322800122080000202400002005120051111600211091010160000100100413111425211717200482201160000102005220052200522005220052
16002420051150045278001212800001280000626400001120032200512005132280012208000020240000200512005111160021109101016000010010041311625211177200572201160000102005220052200522005220052
160024200511510452780012128000012800006264000011200322005120051322800122080000202400002005120051211600211091010160000100100313116252111714200482201160000102005220052200522005220052
16002420051150525452780012128000012800006264000001200412005120051322800122080000202400002005120051111600211091010160000100100413111725421177200482202160000102005220052200522005220052

Test 6: throughput

Count: 16

Code:

  saba v0.8b, v16.8b, v17.8b
  saba v1.8b, v16.8b, v17.8b
  saba v2.8b, v16.8b, v17.8b
  saba v3.8b, v16.8b, v17.8b
  saba v4.8b, v16.8b, v17.8b
  saba v5.8b, v16.8b, v17.8b
  saba v6.8b, v16.8b, v17.8b
  saba v7.8b, v16.8b, v17.8b
  saba v8.8b, v16.8b, v17.8b
  saba v9.8b, v16.8b, v17.8b
  saba v10.8b, v16.8b, v17.8b
  saba v11.8b, v16.8b, v17.8b
  saba v12.8b, v16.8b, v17.8b
  saba v13.8b, v16.8b, v17.8b
  saba v14.8b, v16.8b, v17.8b
  saba v15.8b, v16.8b, v17.8b
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f373a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044007529900054601705025160117100160017100160000500239899904002940039400481997333199971601002001600002004800004003940039111602011009910010016000010000000010110116114003601600001004004040040400404004940040
160204400393000005250004125160117100160000100160000500239899904002040048400391997303200061601002001600002004800004004840039111602011009910010016000010000000010188116114003601600001004004040049400404004940040
1602044003930000024901705025160117100160000114160000500128000004002040039400481997303199971601002001600002004800004004840039111602011009910010016000010000000010110116114004501600001004004040040400404004040040
1602044003930000047701704125160100100160000100160000500128000004002040039400481997303200061601002001600002004800004004840039111602011009910010016000010000000010110116114003601600001004004040049400404004040049
160204400482990005280005025160100100160000100160000500128000004002940039400391997303200061601002001600002004800004003940048111602011009910010016000010000000010110116114003601600001004004040049400494009140049
16020440039300000528017052525160117100160017100160000500128000004002940048400481997303200061601002001600002004800004004840048111602011009910010016000010000000010110116114004501600001004004940049400494004040040
1602044004830000000005025160100100160000100160000500239899904002940048400481997303200061601002001600002004800004003940048111602011009910010016000010000000010110116114004501600001004004040049400404004940040
1602044003930000081301705025160117100160000100160000500128000004002040039400481997303199971601002001600002004800004003940048111602011009910010016000010000000010110116114003601600001004005040040400494004040040
160204400393000005190004125160100100160017100160000500128000004002940048400391997303199971601002001600002004800004004840048111602011009910010016000010000000010110116114004501600001004004940040400494004040049
1602044004830000048301704225160100100160017100160000500239899904002040048400481997303200061601002001600002004800004004840039111602011009910010016000010000000010110116114003601600001004004940040400494004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)18191e1f373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400493010000004625160010101600001016000050128000011400204003940039199963200191600102016000020480000400394003911160021109101016000010000000100223111316211710400450207160000104004040040400494004040040
16002440039299000432004625160010101600001016000050128000011400204003940039199963200191600102016000020480000400494003911160021109101016000010000030100223111016211108400360206160000104004940040400404004040040
160024400392990001800462516001010160000101600005012800001140029400394003919996320019160010201600002048000040039400391116002110910101600001000000010022311916211912400360209160000104004040040400404004040040
160024400393000004020046251600101016000010160000501280000114002040039400671999632001916001020160000204800004004840040111600211091010160000100000001002231112162121084003604012160000104004040040400404004940049
1600244003930000022500462516002710160000101600005012800001140029400394004519996320019160010201600002048000040039400391116002110910101600001000000010022311916212912400360206160000104004040040400404004040040
160024400393000003600046251600101016000010160000501280000114002040039400431999632001916001020160000204800004003940039111600211091010160000100000001002231110162118104004502012160000104004040040400404004040040
16002440039300000192017462516001010160000101600005012800000140020400394005219996320019160010201600002048000040039400391116002110910101600001000200010022311916211119400460206160000104004040040400404004040040
160024400393000002820046651602251216000010160000501280000114020440039400471999632001916001020161367204847434038140597121160021109101016000010202446982102013217126211813404721209160000104065040648406484069540659
160024406173041101013119885411552181611651116124812161431611781057114029640628406142009747203051608492016115420483867407204058414116002110910101600001020006523010254311111174111210406004207160000104082240412407324079540465
160024407403050007201755251600101016001710160000501280000114002040039400431999632001916001020160000204800004003940048111600211091010160000100000001002231112162119124003602012160000104004040040400404004040040