Firestorm: SABA (vector, 8H) measurements

Code:

  saba v0.8h, v1.8h, v2.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	156	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	57	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	111	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2713	1000	3038	3038	3038	3038	3038
1004	3037	23	0	6	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	18	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	267	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	2	16	1	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	342	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  saba v0.8h, v1.8h, v2.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	24	3	3	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	741	1	3	16	3	3	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	710	1	3	16	3	3	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	1	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	4	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	4	16	3	3	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	204	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	0	0	1	78	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	3	0	642	11	16	9	11	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	0	0	0	0	0	1	78	29548	25	10010	10	10000	10	10000	50	4278670	1	30018	30084	30084	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	0	642	6	16	8	9	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	0	0	0	0	0	1	78	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	642	11	16	10	10	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	0	0	0	0	9	2	78	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	642	10	16	9	9	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	0	0	0	0	12	1	78	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	2	0	0	642	7	16	6	8	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	0	0	0	0	0	1	206	29548	25	10010	10	10008	10	10000	50	4280027	0	30018	30037	30180	28287	3	28767	10161	20	10000	22	30000	30084	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	642	9	24	8	9	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	1	0	0	0	0	0	0	1	78	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	642	9	16	7	9	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	0	0	0	0	3	1	78	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	642	7	16	6	7	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	0	0	0	0	0	1	78	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30131	28287	3	28767	10515	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	2	3	0	642	9	16	10	8	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	0	0	0	0	0	1	78	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	642	8	16	8	8	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  saba v0.8h, v0.8h, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	224	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	9	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	726	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	9	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10019	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	1	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	9	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->3

Code:

  saba v0.8h, v1.8h, v0.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	18	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	1	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	6	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	103	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	0	1	732	2	16	2	4	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	3	1	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	4	6	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30498	30037	30037	2	1	10201	100	99	100	100	10000	100	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	552	0	251	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	619	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	26	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30084	224	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30083
10024	30037	225	0	0	0	0	0	124	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  saba v0.8h, v8.8h, v9.8h
  movi v1.16b, 0
  saba v1.8h, v8.8h, v9.8h
  movi v2.16b, 0
  saba v2.8h, v8.8h, v9.8h
  movi v3.16b, 0
  saba v3.8h, v8.8h, v9.8h
  movi v4.16b, 0
  saba v4.8h, v8.8h, v9.8h
  movi v5.16b, 0
  saba v5.8h, v8.8h, v9.8h
  movi v6.16b, 0
  saba v6.8h, v8.8h, v9.8h
  movi v7.16b, 0
  saba v7.8h, v8.8h, v9.8h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20065	151	0	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	1765	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	948	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	1	6	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	2	1	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	3	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	1	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20086	150	1	0	0	0	1	375	25	80012	12	80000	12	80000	62	640000	1	1	5	20029	20048	20048	3	22	80012	20	80000	20	240000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10055	8	1	1	1	41	26	3	2	2	37	37	20060	2	33	0	160000	10	20053	20053	20053	20053	20053
160024	20052	150	1	1	0	0	1	404	25	80012	12	80000	12	80000	62	640000	1	0	5	20033	20048	20052	3	22	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10065	6	2	1	1	38	26	3	2	2	29	37	20049	2	33	0	160000	10	20053	20053	20053	20053	20133
160024	20217	152	1	1	0	0	0	307	25	80012	12	80000	12	80000	62	640000	1	0	0	20033	20052	20052	3	22	80012	20	80000	20	240000	20048	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10062	11	2	2	1	37	26	3	2	2	25	36	20049	2	48	0	160000	10	20053	20053	20053	20053	20053
160024	20048	150	1	1	1	0	0	292	25	80012	12	80000	12	80000	62	640000	0	1	0	20033	20052	20052	3	22	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10062	11	2	2	0	35	26	3	2	2	36	36	20049	2	48	0	160000	10	20053	20053	20049	20053	20053
160024	20052	150	1	1	1	0	1	368	25	80012	12	80000	12	80000	62	640000	1	0	5	20029	20048	20048	3	22	80012	20	80000	20	240000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10060	3	2	1	1	37	22	1	1	1	25	37	20045	2	48	0	160000	10	20049	20049	20049	20049	20049
160024	20048	151	1	1	1	0	1	257	25	80012	12	80000	12	80000	62	640000	1	0	5	20029	20048	20048	3	22	80012	20	80000	20	240000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10060	3	2	1	1	38	22	1	1	1	39	39	20045	2	33	0	160000	10	20049	20049	20049	20049	20049
160024	20048	150	1	1	1	0	1	334	25	80012	12	80000	12	80000	62	640000	1	0	5	20029	20048	20048	3	22	80012	20	80000	20	240000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	6	0	10046	3	1	1	1	37	22	1	1	3	31	35	20045	2	33	0	160000	10	20049	20049	20049	20049	20049
160024	20048	150	1	1	0	0	0	512	25	80012	12	80000	12	80000	62	640000	1	0	5	20029	20048	20048	3	22	80012	20	80000	20	240000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10047	3	2	1	1	26	22	1	1	1	38	38	20045	2	48	0	160000	10	20049	20049	20049	20049	20049
160024	20048	150	1	0	0	0	1	336	25	80012	12	80000	12	80000	62	640000	1	0	5	20029	20048	20048	3	22	80012	20	80000	20	240000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10061	3	2	1	1	30	22	1	1	1	34	36	20045	2	33	0	160000	10	20049	20049	20049	20049	20049
160024	20048	150	1	1	0	0	1	1400	25	80012	12	80000	12	80000	62	640000	1	0	0	20029	20048	20048	3	22	80012	20	80000	20	240000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	3	0	10061	8	1	1	1	37	22	1	1	1	22	37	20045	2	33	0	160000	10	20049	20049	20049	20049	20049

Test 6: throughput

Count: 16

Code:

  saba v0.8h, v16.8h, v17.8h
  saba v1.8h, v16.8h, v17.8h
  saba v2.8h, v16.8h, v17.8h
  saba v3.8h, v16.8h, v17.8h
  saba v4.8h, v16.8h, v17.8h
  saba v5.8h, v16.8h, v17.8h
  saba v6.8h, v16.8h, v17.8h
  saba v7.8h, v16.8h, v17.8h
  saba v8.8h, v16.8h, v17.8h
  saba v9.8h, v16.8h, v17.8h
  saba v10.8h, v16.8h, v17.8h
  saba v11.8h, v16.8h, v17.8h
  saba v12.8h, v16.8h, v17.8h
  saba v13.8h, v16.8h, v17.8h
  saba v14.8h, v16.8h, v17.8h
  saba v15.8h, v16.8h, v17.8h

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	1e	37	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40059	300	0	0	0	0	0	0	41	25	160100	100	160000	100	160000	500	1280000	40020	40048	40039	19973	3	20009	160100	200	160000	200	480000	40048	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40045	0	160000	100	40049	40049	40040	40040	40040
160204	40049	300	0	0	0	0	0	0	41	25	160117	100	160000	100	160000	500	2398999	40020	40039	40049	19973	3	19997	160100	200	160000	200	480000	40039	40048	1	1	160201	100	99	100	100	160000	100	0	1	0	0	0	10110	2	16	2	2	40036	0	160000	100	40040	40041	40049	40040	40040
160204	40039	299	0	0	0	0	0	17	42	25	160117	100	160000	100	160000	500	1280000	40020	40039	40039	19973	3	20006	160100	200	160000	200	480000	40048	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40036	0	160000	100	40049	40040	40040	40049	40040
160204	40048	300	0	0	0	0	0	0	41	25	160100	100	160017	100	160000	500	1280000	40020	40039	40048	19973	3	20006	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40037	0	160000	100	40040	40041	40049	40049	40050
160204	40039	300	0	0	0	0	0	17	50	25	160117	100	160000	100	160000	500	1280000	40030	40040	40040	19973	3	19997	160100	200	160000	200	480000	40048	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	21	0	10110	1	24	2	2	40036	0	160000	100	40040	40040	40041	40049	40040
160204	40048	299	0	0	0	0	0	17	51	25	160117	100	160000	100	160000	500	1280000	40029	40039	40039	19973	3	19997	160100	200	160000	200	480000	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	3	0	10110	2	17	2	2	40036	0	160000	100	40050	40040	40050	40040	40049
160204	40039	299	0	0	0	0	0	0	42	25	160100	100	160017	100	160000	500	1280000	40020	40039	40039	19973	3	19997	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40045	0	160000	100	40040	40049	40049	40040	40049
160204	40039	300	0	0	0	0	15	1	612	25	160117	100	160017	100	160000	500	2398999	40020	40039	40048	19973	3	19997	160100	200	160000	200	480000	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40045	0	160000	100	40040	40049	40049	40040	40040
160204	40048	300	0	0	0	0	0	17	62	25	160117	100	160000	100	160000	500	1280000	40029	40048	40048	19973	3	20006	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40036	0	160000	100	40041	40040	40041	40040	40049
160204	40039	300	0	0	0	0	0	0	41	25	160100	100	160000	100	160000	500	1280000	40029	40048	40048	19973	3	20007	160100	200	160000	200	480000	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40046	0	160000	100	40040	40040	40040	40049	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40049	300	0	0	0	0	0	17	55	25	160010	10	160000	10	160000	50	1280000	1	1	5	40029	0	40048	40039	19996	3	20019	160010	20	160000	20	480000	40048	40048	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	13	4	1	5	16	4	1	1	4	4	40045	20	9	160000	10	40049	40049	40049	40049	40049
160024	40048	299	0	0	0	0	0	17	55	25	160010	10	160000	10	160000	50	2398999	1	1	10	40020	0	40048	40052	19996	3	20028	160010	20	160000	20	480000	40039	40052	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	13	6	1	4	16	8	2	1	3	4	40036	20	9	160000	10	40049	40049	40040	40049	40040
160024	40048	300	0	0	0	0	0	17	55	25	160010	10	160017	10	160000	50	2398999	1	1	10	40029	0	40039	40048	19996	3	20028	160010	20	160000	20	480000	40048	40048	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	13	6	1	4	16	4	1	1	4	4	40046	20	18	160000	10	40049	40040	40049	40049	40040
160024	40039	300	0	0	0	0	0	0	55	25	160010	10	160000	10	160000	50	1280000	1	1	10	40029	0	40039	40048	19996	3	20029	160010	20	160000	20	480000	40048	40048	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	13	6	1	3	16	8	1	1	4	4	40045	20	9	160000	10	40040	40049	40040	40049	40049
160024	40048	300	0	0	0	0	0	17	46	25	160010	10	160000	10	160000	50	2398999	3	1	10	40029	0	40039	40039	19996	3	20019	160010	20	160000	20	480000	40048	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	13	6	1	4	16	8	1	1	4	4	40045	20	9	160000	10	40049	40040	40049	40040	40040
160024	40048	300	0	0	0	0	0	17	46	25	160010	10	160000	10	160000	50	2398999	1	1	10	40020	0	40039	40048	19996	3	20028	160010	20	160000	20	480000	40039	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	13	6	1	4	16	4	1	1	4	3	40036	20	9	160000	10	40040	40049	40049	40040	40040
160024	40048	300	0	0	0	0	0	17	55	25	160010	10	160000	10	160000	50	1280000	1	1	10	40029	0	40039	40048	19996	3	20019	160010	20	160000	20	480000	40048	40048	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	13	6	1	4	16	4	1	1	4	4	40036	20	9	160000	10	40049	40040	40049	40049	40040
160024	40039	300	0	0	0	0	0	0	55	25	160027	10	160000	10	160000	50	1280000	1	1	10	40029	0	40039	40048	19996	3	20028	160010	20	160000	20	480000	40048	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	13	6	1	4	16	4	1	1	3	4	40045	20	9	160000	10	40049	40040	40049	40040	40040
160024	40039	300	0	0	0	0	0	17	76	25	160027	10	160017	10	160000	50	1280000	1	1	10	40030	0	40039	40052	19996	3	20028	160010	20	160000	20	480000	40048	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	13	6	1	3	16	8	1	1	4	4	40045	20	9	160000	10	40049	40049	40049	40049	40049
160024	40039	300	0	0	0	0	0	0	46	25	160027	10	160017	10	160000	50	2398999	1	1	10	40020	0	40048	40048	19996	3	20019	160010	20	160000	20	480000	40039	40045	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	13	6	1	4	16	8	1	1	4	3	40045	20	9	160000	10	40049	40049	40040	40049	40040

SABA (vector, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations