Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SABDL2 (vector, 2D)

Test 1: uops

Code:

  sabdl2 v0.2d, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723000612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303723000612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303723000612548251000100010003983131301830373037241532895100010002000303730371110011000073116212630100030383038303830383038
10043037230002912548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303723000612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303722000612548251000100010003983131301830373037241532895100010002000303730371110011000073116212630100030383038303830383038
1004303723000612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303723001612548251000100010003983131301830373037241532895100010002000303730371110011000073116112702100030383038303830383038
1004303723000822548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303722000612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  sabdl2 v0.2d, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722546261295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001001307101161129634100001003003830038300383003830038
1020430037225061295482510100100100001041000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282683287451025420010000200200003003730037211020110099100100100001001007101161129634100001003003830038300383003830038
1020430037225061295484410130100100001001000050042800271300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000307101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372240156295482510010101000010100005042773131300183003730037282903287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300653003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002530037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003721100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722402746295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  sabdl2 v0.2d, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500612954825101001001000010010000500427731313001830037300372826503287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826503287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010149643427731303001830037300372826503287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826503287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826503287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826503287451010020010000200203603003730037111020110099100100100001000007101161129707100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826503287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500612954825101341001000010010000500427731313001830037300372826503287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826503287451010020010000200200003003730037111020210099100100100001000007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826503287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372240612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010001640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103022730038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  sabdl2 v0.2d, v8.4s, v9.4s
  sabdl2 v1.2d, v8.4s, v9.4s
  sabdl2 v2.2d, v8.4s, v9.4s
  sabdl2 v3.2d, v8.4s, v9.4s
  sabdl2 v4.2d, v8.4s, v9.4s
  sabdl2 v5.2d, v8.4s, v9.4s
  sabdl2 v6.2d, v8.4s, v9.4s
  sabdl2 v7.2d, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420059150004125802081008000010080000500640000120020200392003999733999780100200800982001600002003920039118020110099100100800001001051103161120036800001002004020040200402004020040
8020420039150004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
8020420039150004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
8020420039150008325801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001002051101161120036800001002004020040200402004020040
8020420039150004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001001051101161120036800001002004020040200402004020040
8020420039150008325801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001003051101161120036800001002004020040200402004020040
8020420039150004125801001008000010480000500640000120020200982003999737999780100200802072001600002003920039118020110099100100800001001051101161120036800001002004020249200402004020040
8020420039151004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
8020420039150008325801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
8020420039150004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03091e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acbranch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000005020241624252003600080000102004020040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000005020281627272003600080000102004020040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000005020201627212003600080000102004020040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000005020291614272003600080000102004020040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000020005020161627192003600080000102004020040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000009005020161627212003600080000102004020040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000005020221627132003600080000102004020040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000010005020161627222003600080000102004020040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000005020261628282003600080000102004020040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000005020271626272003600080000102004020040202412004020040