Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SABDL2 (vector, 4S)

Test 1: uops

Code:

  sabdl2 v0.4s, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037220061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037230061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037220061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037220061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037220061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037230061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037230061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037220061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037230061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037220061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  sabdl2 v0.4s, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500612954825101001001000010010000500427731313001830037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225000612953025100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300811110021109101010000103000640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000101000640216422963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  sabdl2 v0.4s, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225020027922953925101001001000010010149500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010020071011611296340100001003003830038300383003830038
1020430037225011208229548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100019710116112963414100001003003830038300383003830038
102043003722500088612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372240000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071012511296340100001003003830038300383003830038
1020430037225008705362954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372240000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731313001830084300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250054061295482510010101000010100005042773133001803003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722400237061295482510010101000010100005042773133001803003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250024061295482510010101000010100005042773133001803003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225001260222295482510010101000010100005042773133001803003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250018061295482510010101000010100005042773133001803003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225026082295482510010101000010100005042773133001803003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250018061295482510010101000010100005042773133001803003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372240039061295482510010101000010100005042773133001803003730037282873287671001020100002020324300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722500435061295482510010101000010100005042773133001803003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250000251295482510010101000010100005042773133001803003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  sabdl2 v0.4s, v8.8h, v9.8h
  sabdl2 v1.4s, v8.8h, v9.8h
  sabdl2 v2.4s, v8.8h, v9.8h
  sabdl2 v3.4s, v8.8h, v9.8h
  sabdl2 v4.4s, v8.8h, v9.8h
  sabdl2 v5.4s, v8.8h, v9.8h
  sabdl2 v6.4s, v8.8h, v9.8h
  sabdl2 v7.4s, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003915010025504125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000000511021611200360800001002004020040200402004020040
80204200391500003904125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000000511011611200360800001002004020040200402004020040
8020420039150000004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000000511011611200360800001002004020040200402004020040
8020420039150000004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000000511011611200360800001002004020040200402004020040
8020420039150000004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000000511011611200360800001002004020040200402004020040
802042003915000024041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000000540511011611200360800001002004020040200402004020040
8020420039150000004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000000511011611200360800001002004020040200402004020040
802042003915000042604125801001008000010080000500640000020069200392003999733999780100200800002001600002003920039118020110099100100800001000000000511011611200360800001002004020040200402004020040
8020420039150000537070625801001008000010080000500640000020020200392003999733999780100200801042001600002003920039118020110099100100800001000000000511011611200360800001002004020040200402004020040
8020420039150000004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000000511011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200401500000040258001010800001080000506400000020020020039200399996310019800102080000201600002003920039118002110910108000010000502000015160001714200360080000102004020040200402004020040
80024200391500000040258001010800001080000506400000020020020039200399996310019800102080000201600002003920039118002110910108000010000502000016160001617200360080000102004020040200402004020040
8002420039150002100402580010108000010800005064000001200200200392003999962710019800102080000201600002003920039118002110910108000010000502000016160001618200360080000102004020040200402004020040
80024200391500000040258001010800001080000506400000120020020039200399996310019800102080000201600002003920039118002110910108000010000502000017160001417200360080000102004020040200402004020040
8002420039150000352040258001010800001080000506400000120020020039200399996310019800102080000201600002003920039118002110910108000010000502000017160001415200360080000102004020040200402004020040
80024200391500015004025800101080000108000050640000012002002003920039999631001980010208000020160000200392003911800211091010800001000050200001716000917200360080000102004020040200402004020040
80024200391500000040258001010800001080000506400000120020020039200399996310019800102080000201600002003920039118002110910108000010000502000017160001417200360080000102004020040200402004020088
80024200391500000040258001010800001080000506400000120020020039200399996310019800102080000201600002003920039118002110910108000010000502000017160001716200360080000102004020040200402004020040
80024200391500000040258001010800001080000506400000120020320039200399996310019800102080000201600002003920039118002110910108000010000502000014160001716200360080000102004020040200402004020040
800242003915000120040258001010800001080000506400000120020020039200399996310019800102080000201600002003920039118002110910108000010000502000017160001717200360080000102004020040200402004020040