Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SABDL2 (vector, 8H)

Test 1: uops

Code:

  sabdl2 v0.8h, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073216112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372266125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  sabdl2 v0.8h, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500061295482510100100100001001000050042773130300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773130300180300373003728265328745101002001000020020000300373003711102011009910010010000100000289807101161129634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773130300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773130300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
102043003722509061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773130300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
102053003722500061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100020607101161129634100001003003830038301233008430038
1020430037225012061295482510100104100001001000050042786351300180300373003728265328745102722001000020020000300373003721102011009910010010000100010007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006404162229630010000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100028916402162229630010000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037224000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383008530038
1002430037224000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722500000117029548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  sabdl2 v0.8h, v1.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372240103295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373008511102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037224061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372256129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722561295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010100640216222963010000103003830038300383003830038
10024300372256129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372256129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372246129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383008530038
10024300372256129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001003640216222963010000103003830038300383003830038
10024300372256129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372246129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372256129530251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372246129530251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  sabdl2 v0.8h, v8.16b, v9.16b
  sabdl2 v1.8h, v8.16b, v9.16b
  sabdl2 v2.8h, v8.16b, v9.16b
  sabdl2 v3.8h, v8.16b, v9.16b
  sabdl2 v4.8h, v8.16b, v9.16b
  sabdl2 v5.8h, v8.16b, v9.16b
  sabdl2 v6.8h, v8.16b, v9.16b
  sabdl2 v7.8h, v8.16b, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150000852580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051102161120036800001002004020040200402004020040
80204200391500012412580100100800001008000050064000020020200392003999733999780100200800002001600002014220039118020110099100100800001000051101161120036800001002004020040200402004020040
8020420039150000832580100100800001008000050064000020020200392003999733999780100200800002001600002008920039118020110099100100800001000051102161120036800001002004020091200402004020040
8020420039150000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001001051101161120036800001002004020040200402004020040
802042003915000181882580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
8020420039150000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
8020420039150000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
8020420039150000832580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001001051101161120036800001002004020040200402004020040
8020420039150000622580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020045
8020420039150100622580100100800001008000050064000020020200392003999733999780100200801072001600002003920039218020110099100100800001000651101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)091e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915000004025800101080000108000050640000102002020039200399996310019800102080000201600002003920039118002110910108000010050210001181600817200360080000102004020040200402004020040
8002420039150110086258001010800001080000506400001020020200392003999963100198001020800002016000020039200391180021109101080000100502100011216001714200360080000102004020040200402004020040
8002420039150110086258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000100502100011416001710200360080000102004020040200402004020040
800242003915011008225800101080000108000050640000102002020039200399996310019800102080000201600002003920039118002110910108000010050210001171600917200360080000102004020040200402004020040
8002420039150000014925800101080000108000050640000102002020039200399996310019800102080000201600002003920039118002110910108000010050210001101600178200360080000102004020040200402004020040
8002420039150110086258001010800001080000506400001020020200392003999963100198001020800002016000020039200391180021109101080000101502100011716001017200360080000102004020040200402004020040
80024200391501100128258001010800001080000506400001020020200392003999963100198001020800002016000020039200391180021109101080000100502100011816001715200360080000102004020040200402004020040
8002420039150110012825800101080000108000050640000102002020039200399996310019800102080000201600002003920039118002110910108000010050210001816001417200360080000102004020040200402004020040
8002420039150110086258001010800001080000506400001020020200392003999963100198001020800002016000020039200391180021109101080000100502100011816001717200360080000102004020040200402004020040
8002420039150110086258001010800001080000506400001020020200392003999963100198001020800002016000020039200391180021109101080000100502100011716001717200360080000102004020040200402004020040