Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SABDL (vector, 4S)

Test 1: uops

Code:

  sabdl v0.4s, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037230612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037239612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037230612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
100430372301032548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037230612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037220612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037230612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037230612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037230612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  sabdl v0.4s, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372240000081295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100000000000071011611296340100001003003830038300383003830038
102043003722500000726295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100000000000071011611296340100001003003830038300383003830038
102043003722500000726295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100000000000071011611296340100001003003830038300383003830038
102043003722500000251295482510100100100001001000050042773131300183003730037282650328745101002001049420020000300373003711102011009910010010000100000000000071011611296340100001003003830038300383003830038
102043003722500000726295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100000000000071011611296340100001003003830038300383003830038
10204300372250000061295482510100100100001001000050042773131300183003730037282650328745101002041016420620330300853008421102011009910010010000100220002825200073213311296700100001003003830038300383003830038
102043003722500089706129548451010010010000103102985814280027130018300373003728265032874510100200100002002000030037300371110201100991001001000010092100141180000825464112977521100001003032330085303123027630274
102043032522513452826461295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100000000000071011611296340100001003003830038300383003830038
10204300372250000061295482510100100100001001000050042773130300183003730037282650328745101002101000020020000300373003711102011009910010010000100000000000071011612296340100001003003830038300383003830038
102043003722500000229295482510100100100001001000050042777971300183003730037282650328745101002001000020020000300373003711102011009910010010000100000000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250612954825100101010000101000050427731313001803003730037282870328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001803003730037282870328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001803003730037282870328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372240612954825100101010000101000050427731303001803003730037282870328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001803003730037282870328767100102410000202067030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773131300180300373003728287032876710010201000020200003003730037111002110910101000010159640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001803003730037282870328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001803003730037282870328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001803003730037282870328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001803003730037282870328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  sabdl v0.4s, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318193f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003013230038300383008530038
10204300372258861295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001004071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)1e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000061295482510010101000010100005042773131300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773131300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773131300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037224000061295482510010101000010100005042773131300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773131300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773131300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773131300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037227000061295482510010101000010100005042773131300183003730037282870328767100102010000202000030037300371110021109101010000100000640116222963010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773131300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037224000061295482510010101000010100005042773131300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  sabdl v0.4s, v8.4h, v9.4h
  sabdl v1.4s, v8.4h, v9.4h
  sabdl v2.4s, v8.4h, v9.4h
  sabdl v3.4s, v8.4h, v9.4h
  sabdl v4.4s, v8.4h, v9.4h
  sabdl v5.4s, v8.4h, v9.4h
  sabdl v6.4s, v8.4h, v9.4h
  sabdl v7.4s, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010051102161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200392180201100991001008000010051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010051101161120036800001002004020040200402004020040
802042003915010241258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010051101161120036800001002004020040200402004020040
80204200391503941258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400001200592003920039997339997801002008000020016000020039200391180201100991001008000010051101161120036800001002004020040200402004020107
8020420039150041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010051101161120036800001002004020040200402004020040
802042003915033341258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815500040258001010800001080000606400000002002020039200399996310019800102080000201600002003920039118002110910108000010050202162220036080000102004020040200402004020040
800242003915000040258001010800001080000506400000002002020039200399996310019800102080000201600002003920039118002110910108000010050202162220036080000102004020040200402004020040
800242003915000040258001010800001080000506400000002002020039200399996310019800102080000201600002003920039118002110910108000010650202162220036080000102004020040200402004020040
800242003915000640258001010800001080000506400000002002020039200399996310019800102080000201600002003920039118002110910108000010050203163220036080000102004020040201122004020040
8002420039150000402580010108000010800005064000000020020200392003999963100198001020800002016000020039200391180021109101080000100502031634200362280000102004020040200402004020040
8002420039150006230258001010800001080000506400000012002020039200399996310019800102080000201600002003920039118002110910108000010050203164220036080000102004020040200402004020040
800242003915000040258001010800001080000506400000002002020039200399996310019800102080000201600002003920039118002110910108000010050202162220036080000102004020040200402004020040
800242003915000040258001010800001080000506400000002002020039200399996310019800102080000201600002003920039118002110910108000010050202162220036080000102004020040200402004020040
800242003915000640258001010800001080000506400000002002020039200399996310019800102080000201600002003920039118002110910108000010050202162220036080000102004020040200402004020040
800242003915000040258001010800001080000506400000002002020039200399996310019800102080000201600002003920039118002110910108000010050202163420036080000102004020040200402004020040