Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SABDL (vector, 8H)

Test 1: uops

Code:

  sabdl v0.8h, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372215361254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303723061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303723061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303723061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303722061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303722061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303723061254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303723061254825100010001000398313301830373037241532895100010002000303730371110011000173116112630100030383038303830383038
1004303723082254825100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303722061254844100010001000398313301830373037241532895100010002000303730371110011000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  sabdl v0.8h, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000071001161129634100001003003830038300383003830038
102043003722501061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000224871001161129634100001003003830038300383003830038
102043003722510053629548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000071001161129634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000071001161129634100001003003830038300383003830038
10204300372250006129548251010010010008100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100004071001161129937100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100003071001161129634100001003003830038300383003830038
10204300372240006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100023071001161129667100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100002071001161129634100001003003830038300383003830038
102043003722500396129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000071001161129634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100003071001161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
1002430037224061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
1002430037225061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630210000103003830038300383003830038
1002430037225061295482510010101000010100005042786703001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
1002430037224061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
1002430037224061295482510010101000010100005042773133001830037300372828732878210010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250726295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
1002430037225061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010106402162229630010000103003830038300383003830038
1002430037225061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
1002430037224061295482510010101000010100005042773133005230037300372830732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  sabdl v0.8h, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500612954825101001001000010010000500427731303001830037300372827272874110100200100082002001630037300371110201100991001001000010000011171801600296470100001003003830038300383003830038
102043003722400612954825101001001000010010000500427731313001830037300372827262874010100200100082002001630037300371110201100991001001000010000011171701600296460100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372827272874010100200100082002001630037300371110201100991001001000010000011171701600296460100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728272628740101002001000820020016300373003711102011009910010010000100000111717016002964721100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372827272874010100200100082002001630037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003722400612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010020000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003722500612954825101001241000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225006129548251001010100001010000504277313103001830037300372828732876710010201000020200003003730037111002110910101000010000064000216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313003001830037300372828732876710010201000020200003003730037111002110910101000010000067000216222963010000103003830038300383003830038
100243003722500174829548251001010100001010000504277313003001830037300372828732876710010201000020200003003730037111002110910101000010000064000216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313003001830037300372828732876710010201000020200003003730037111002110910101000010000064000216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313103001830037300372828732876710010201000020200003003730037111002110910101000010000064000216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313103001830037300372828732876710010201000020200003003730037111002110910101000010000064000216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313003001830037300372828732876710010201000020200003003730037111002110910101000010000064000216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277735103001830037300372828732876710010201000020200003003730037111002110910101000010000064000216222963010000103003830038300383003830038
10024300372250072629548251001010100001010000504277313103001830037300372828732876710010201000020200003003730037111002110910101000010010064000216222963010000103003830038300383003830038
100243003722500178929548251001010100001010000504277313003001830037300372828732876710010201000020200003003730037111002110910101000010000064000216222963010000103003830038300383008530038

Test 4: throughput

Count: 8

Code:

  sabdl v0.8h, v8.8b, v9.8b
  sabdl v1.8h, v8.8b, v9.8b
  sabdl v2.8h, v8.8b, v9.8b
  sabdl v3.8h, v8.8b, v9.8b
  sabdl v4.8h, v8.8b, v9.8b
  sabdl v5.8h, v8.8b, v9.8b
  sabdl v6.8h, v8.8b, v9.8b
  sabdl v7.8h, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200601500004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010002005110216112003612800001002004020040200402004020040
802042003915000010052580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040
80204200391500005022580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040
802042003915000041258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100001710511011611200360800001002004020040200402004020040
8020420039150000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040
8020420039150000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040
80204200391500004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000360511011611200360800001002004020040200402004020040
80204200391500001084258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100001530511011611200360800001002004020040200402004020040
8020420039150000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040
8020420039150000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)daddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004015001222580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000050204160552003680000102004020040200402004020040
800242003915006422580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000050203160362003680000102004020040200402004020040
8002420039150012202580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000050205160532003680000102004020040200402004020040
800242003915004462580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000050205160532003680000102004020040200402004020040
8002420039150040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000144050205160532003680000102004020040200402004020040
80024200391500402580010108000010800005064000002002020039200399996310019800102080000201600002003920039218002110910108000010000050205160552003680000102004020040200402004020040
800242003915004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100012050205160532003680000102004020040200402004020040
8002420039150013525800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100057050203160652003680000102004020040200402004020040
80024200391500462580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000050205160532003680000102004020040200402004020040
80024200391500462580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000050205160542003680000102004020040200402004020040