Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SABD (vector, 4S)

Test 1: uops

Code:

  sabd v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723096625482510001000100039831313018303730372415328951000100020003037303711100110000073216112630100030383038303830383038
1004303723006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230061254825100010001000398313130183037303724153289510001000200030373037111001100010073116112630100030383038303830383038
1004303723006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  sabd v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007102161129634100001003003830038300383003830038
1020430037225025129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100307101161129634100001003003830038300383003830038
1020430037225015629548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225044129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225072629548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402172229630010000103003830038300383003830038
10024300372240061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373008411100211091010100001006402162229630110000103003830038300383003830038
100243003722500726295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250061295482510010101000810100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372251061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  sabd v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250612954825101241001000010010000500427731330018300373003728265328745102602001000020020000300373003711102011009910010010000100000071011611296650100001003003830038300383003830038
102043003722512612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372240612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731330018300373003728265328745101002081000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731330018300373003728265328745101002001000020420000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372240612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372240612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038301343003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000000061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731330018300373003728287828858109072411100242098230318303218110021109101010000104021216665207905643229810310000103037130274302283037130368
10024303222250016706164567294851611007216100081411043944286812302703037030366283173128825110582211150222228030132303676110021109101010000104031019410407842853329900510000103037030366303693036930122
1002430366227110779336164881294851641007218100561410149874286812302343017930416283103428898106102010984242229230369302247110021109101010000102403020510006402162229630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300863008630038
1002430037225000000061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000100006402162229630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  sabd v0.4s, v8.4s, v9.4s
  sabd v1.4s, v8.4s, v9.4s
  sabd v2.4s, v8.4s, v9.4s
  sabd v3.4s, v8.4s, v9.4s
  sabd v4.4s, v8.4s, v9.4s
  sabd v5.4s, v8.4s, v9.4s
  sabd v6.4s, v8.4s, v9.4s
  sabd v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200601500412580100100800001008000050064000013200202003920039997339997801002008000020016000020039200391180201100991001008000010020511003162220036800001002004020040200402004020040
80204200391500622580100100800001008000050064000010200202003920039997339997801002008000020016000020039200391180201100991001008000010000511032162220036800001002004020040200402004020040
80204200391500412580100100800001008000050064000003200202003920039997339997801002008000020016000020039200391180201100991001008000010000511002162220036800001002004020040200402004020040
802042003915004125801001008000010080000500640000102002020039200399973399978010020080000200160000200392003911802011009910010080000100078511002162220036800001002004020040200402004020040
802042003915004125801001008000010080000500640000032002020039200399973399978010020080000200160000200392003911802011009910010080000100075511002162220036800001002004020040200402004020040
80204200391500412580100100800001008000050064000010200202003920039997339997801002008000020016000020039200391180201100991001008000010000511032162220036800001002004020040200402004020040
80204200391500412580100100800001008000050064000013200202003920039997339997801002008000020016000020039200391180201100991001008000010000511032162220036800001002004020040200402015420040
802042003915004125801001008000010080000500640000102002020039200399973399978010020280000200160000200392003911802011009910010080000100093511032162220036800001002004020040200402004020040
802042003915001542580100100800001008000050064000003200202003920039997339997801002008000020016000020039200391180201100991001008000010000511032162220036800001002004020040200402004020040
80204200391500412580100100800001008000050064000003200202003920039997339997801002008000020016000020039200391180201100991001008000010000511002162220036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfl1i cache miss demand (d3)d5map dispatch bubble (d6)daddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150004025800101080000108000050640000120020020039200399996310019800102080000201600002003920039118002110910108000010000502001160112003680000102004020040200402004020040
8002420039150004025800101080000108000050640000120020020039200399996310019800102080000201600002003920039118002110910108000010100502001160112003680000102004020040200402004020040
8002420039150004025800101080000108000050640000120020020039200399996310019800102080000201600002003920039118002110910108000010000502001160112003680000102004020040200402004020040
8002420039150004025800101080000108000050640000120020020039200399996310019800102080000201600002003920039118002110910108000010100502001160112003680000102004020040200402004020040
80024200391500013525800101080000108000050640000020020020039200399996310019800102080000201600002003920039118002110910108000010000502001160112003680000102004020040200402004020040
8002420039150004025800101080000108000050640000120020020039200399996310019800102080000201600002003920039118002110910108000010000502001160112003680000102004020040200402004020040
8002420039150004025800101080000108000050640000120020020039200399996310019800102080000201600002003920039118002110910108000010000502001160112003680000102004020040200402004020040
8002420039150004025800101080000108000050640000020020020039200399996310019800102080000201600002003920039118002110910108000010000502001160112003680000102004020040200402004020040
8002420039150004025800101080000108000050640000120020020039200399996310019800102080000201600002003920039118002110910108000010000502001160112003680000102004020040200402004020040
8002420039150004025800101080000108000050640000120020020039200399996310019800102080000201600002003920039118002110910108000010000502001160112003680000102004020040200402004020040