Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SABD (vector, 8B)

Test 1: uops

Code:

  sabd v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037220612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220612548251000100010003983133018303730372415328951000100020003037303711100110001073116112630100030383038303830383038
100430372303652548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110001073116112630100030383038303830383038
100430372301052548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110001073116112630100030383038303830383038
100430372201512548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  sabd v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225061295482510100100100001001000050042773130030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037233061295482510100100100001001000050042773130030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773130030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037224361295482510100100100001001000050042773130030018300373003728265328745101002001000020020000300373003711102011009910010010000100107101161129634100001003003830038300383003830038
10204300372240126295482510100100100001001000050042773130030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037232061295482510100100100001001000050042773130030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037224061295482510100100100001001000050042773131030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773130030018300373003728265328745101002001000020020000300373003711102011009910010010000100207101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000064842773130030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773130030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250028129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300853003830038
1002430037224006129548251001010100001010000504277313130018300373003728287032876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037232006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018300373003728287032876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287032876710010201000020203443003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018300373003728287032876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037224006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  sabd v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250006129548251010010010000100100005004277313030018300373003728265032874510100200100002002000030037300371110201100991001001000010000000710011611296340100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313130018300373003728265032874510100200100002002000030037300371110201100991001001000010000000710011611296340100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313030018300373003728265032874510100200100002002000030037300371110201100991001001000010000000710011611296340100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313030018300373003728265032874510254200100002002000030037300371110201100991001001000010000000710011611296340100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313030018300373003728265032874510100200100002002000030037300371110201100991001001000010000000710011611296340100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313030018300373003728265032874510100200100002002000030037300371110201100991001001000010000000710011611296340100001003003830038300383003830038
102043003722500072629548251010010010000100100005004277313030018300373003728265032874510100200100002002000030037300371110201100991001001000010000000710011611296340100001003003830071300383003830038
10204300372250006129548251010010010000100100005004277313030018300373003728265032874510100200100002002000030037300371110201100991001001000010000000710011611296340100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313030018300373003728265032874510100200100002002000030037300371110201100991001001000010000000710011611296340100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313030018300373003728265032874510100200100002002000030037300371110201100991001001000010000000710011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243027423501003020129548251001010100001010000504277313030018300373003728287328767100102010012202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
100243003722500000015629548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100306403163329630010000103003830038300383003830038
100243003722500000072629548251001010100001010000504277313030018300373003728287328767101602010000202032630085300371110021109101010000100307944403629918410000103040630133304163021630407
100243041422711385317042604295121791004915100241311192784287729030018300373003728287328767100102010000202000030084300371110021109101010000100008093813329924010000103041730227304613017930460
1002430132225000000612954825100101010000101000086428816903027030170304622832439288371048720113122220978304613022410110021109101010000100006403985429882310000103046130321304153046730369
10024301322250000177061295482510010101000010105781194285455030018300373003728287328767101632010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
10024300372240000606129548251001010100001010000504277313130018300373003728287328767100102010000202033630037300371110021109101010000100006403163329630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  sabd v0.8b, v8.8b, v9.8b
  sabd v1.8b, v8.8b, v9.8b
  sabd v2.8b, v8.8b, v9.8b
  sabd v3.8b, v8.8b, v9.8b
  sabd v4.8b, v8.8b, v9.8b
  sabd v5.8b, v8.8b, v9.8b
  sabd v6.8b, v8.8b, v9.8b
  sabd v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150090325801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051104162320036800001002004020040200402004020040
802042003915001038258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000012051102163220036800001002004020040200402004020040
802042003915004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051102162320036800001002004020040200402004020040
802042003915004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000003051102162320036800001002004020040200402004020040
802042003915004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000003051103163220036800001002004020040200402004020040
802042003915004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051103163320036800001002004020040200402004020040
802042003915004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000003051102163320036800001002004020040200402004020040
802042003915004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000009251102163320036800001002034920040200402004020074
80204200391500983258010010080000100800005006400000200672009820099997389997801002008000020016000020039200391180201100991001008000010043000511042843320075800001002010020100200402017420116
802042003915004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000051103162320036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815011212425800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100050240181622182003680000102004020040200402004020040
80024200391501124725800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100050240201617222003680000102004020040200402004020040
800242003915011247258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001009650240211618212003680000102004020040200402004020040
80024200391501124725800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100050240151619172003680000102004020040200402004020040
800242003915011516025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100050240221618222003680000102004020040200402004020040
80024200391501125325800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100050240181622152003680000102004020040200402004020040
80024200391501121004258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001003650243181612232003680000102004020040200402004020040
8002420039150112532580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010015050240211622222003680000102009120040200402004020040
80024200391501125325800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100050240111622132003680000102004020040200402004020040
80024200391501125325800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100050240201621212003680000102004020040200402004020040