Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SABD (vector, 8H)

Test 1: uops

Code:

  sabd v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)accfd5map dispatch bubble (d6)dbddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000732160222630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000732160222630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000732160222630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000732160222630100030383038303830383038
1004303722025125482510001000100039831313018303730372415328951000100020003037303711100110003732160222630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000732160222630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000732160222630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000732160222630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000732160222630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000732160222630100030383038303830383038

Test 2: Latency 1->2

Code:

  sabd v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722501031295482510100100100001001000050042773130300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
10204300372250166295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
10204300372250187295482510100100100001001000050042773130300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
10204300372250879295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
10204300372240507295482510100100100001001000050042773130300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
10204300372250996295482510100100100001001000050042773130300180300373003728265328745101002001000020020000300373003711102011009910010010000100040007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
10204300372250903295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
10204300372250946295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
10204300372250944295482510100100100001001000050042773130300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500088129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722500079129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100296800640216222963010000103003830038300383003830038
1002430037225000145629548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722500026129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722500090529548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722500066229548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722500084629548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243008422400060529548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722500097529548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  sabd v0.8h, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000052242773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250061295482510125100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300180300373003728265328745101002001016320620000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372261061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225006129548251001010100001010000504277313130018030037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018030037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018030037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018030037300372828732876710010201000020200003003730037111002110910101000010000016402162229630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018030037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018030037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018030037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018030037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018030037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225006129530251001010100001010000504277313130018030037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  sabd v0.8h, v8.8h, v9.8h
  sabd v1.8h, v8.8h, v9.8h
  sabd v2.8h, v8.8h, v9.8h
  sabd v3.8h, v8.8h, v9.8h
  sabd v4.8h, v8.8h, v9.8h
  sabd v5.8h, v8.8h, v9.8h
  sabd v6.8h, v8.8h, v9.8h
  sabd v7.8h, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581500412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051105261120036800001002004020040200402004020040
80204200391500412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
802042003915033832580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
80204200391500412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
80204200391500412580100100800001008000050064000002002020039200399973399978010020080000200160638200392003911802011009910010080000100051101161120036800001002004020040200402004020040
80204200391500412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
80204200391500412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
80204200391500412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
80204200391500412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200432015020040
80204200391500412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150002142580010108000010800005664000012002020039200399996031001980010208000020160000200392003911800211091010800001000502002416142420036080000102004020040200402004020040
800242003915000402580010108000010800005064000002002020039200399996031001980010208000020160000200392003911800211091010800001000502002516152520036080000102004020040200402004020040
80024200391500012272580010108000010800005064000002002020039200399996031001980010208000020160000200392003911800211091010800001000502001416261520036080000102004020040200402004020040
800242003915000402580010108000010800005064000012002020039200399996031001980010208000020160000200392003911800211091010800001000502002416212520036080000102004020040200402004020040
800242003915000402580010108000010800005064000012002020039200399996031001980010208000020160000200392003911800211091010800001000502001616261620036080000102004020040200402004020040
800242003915000402580010108000010800005064000012002020039200399996031001980010208000020160000200392003911800211091010800001000502002816272720036080000102004020040200402004020040
800242003915000402580010108000010800005064000002002020039200399996031001980010208000020160000200392003911800211091010800001000502002816142720036080000102004020040200402004020040
800242003915000402580010108000010800005064000002002020039200399996031001980010208000020160000200392003911800211091010800001000502031416272120036080000102004020040200402004020040
800242003915000402580010108000010800005064000012002020039200399996031001980010208000020160000200392003911800211091010800001000502001216251420036080000102004020040200402004020040
8002420039150001035080010108000010800005064000012002020039200399996031001980010208000020160000200392003911800211091010800001000502002716282820036080000102004020040200402004020040