Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SADALP (vector, 1D)

Test 1: uops

Code:

  sadalp v0.1d, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073216112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
10043037230612548251000100010003983130301830373037241532895100010002000303730371110011000021073116112630100030383038303830383038
10043037230612548251000100010003983130301830373037241532895100010002000303730371110011000012073116112630100030383038303830383038
1004303723061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
10043037230612548251000100010003983130301830373037241532895100010002000303730371110011000015073116112630100030383038303830383038
1004303722061254825100010001000398313030183037303724153289510001000200030373037111001100001073116112630100030383038303830383038
1004303722061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  sadalp v0.1d, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722533892954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722530612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225337262954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300372110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372827732874510100200100002002000030037300371110201100991001001000010000071012511296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250842954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011603296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372240612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722506129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100221091010100001000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722406129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  sadalp v0.1d, v0.2s
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372411010061295472510100100100001001000050042771601300183003730037282716287401010020010008200200163003730037111020110099100100100001000001117171161129648100001003003830038300383003830038
10204300372411010061295472510100100100001001000050042771600300183003730037282717287411010020010008200200163003730037111020110099100100100001000131117181161129647100001003003830038300873003830038
10204302252411010061295472510100100100001001000050042771600300183003730037282716287401010020010008200200163003730037111020110099100100100001000001117171161129647100001003003830038300383003830038
10204300372411010061295472510100100100001001000050042771601300183003730037282716287411010021210008200200163003730037111020110099100100100001000028581117171161129648100001003003830038300383003830038
10204300372321010061295472510100100100001001000050042771600300183003730037282716287401010020010008200200163003730037111020110099100100100001000001117171161129647100001003003830038300383003830038
10204300372331010061295472510100100100001001000050042771600300183003730037282716287401010020010008200200163003730037111020110099100100100001000001117171161129648100001003003830038300383003830038
10204300372291010061295472510100100100001001000050042771601300183003730037282716287411010020010008200200163003730037111020110099100100100001000001117171161129647100001003003830038300383003830038
10204300372291010061295472510100100100001001000050042771601300183003730037282716287401010020010008200200163003730037111020110099100100100001000001117181161129647100001003003830038300383003830038
10204300372291010061295472510100100100001001000050042771600300183003730037282716287411010020010008200200163003730037111020110099100100100001000001117171161129647100001003003830038300383003830038
1020430037225101001106295472510100100100001001000050042771601300183003730037282716287411010020010008200200163003730037111020110099100100100001000001117171161129647100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000640216222962910000103003830038300383003830038
1002430037225000061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000640216222962910000103003830038300383003830038
1002430037225000061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000640216222962910000103003830038300383003830038
1002430037225000061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000640216222962910000103003830038300383003830038
10024300372250030061295472510010101000010100005042771601300183022730037282863287671001020100002020000300373003711100211091010100001000640216222962910000103003830038300383003830038
1002430037224000061295472510010101000010100005042771601300183003730037282863287671007220100002020000300373003711100211091010100001000640216222962910000103003830038300383003830038
1002430037225000061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000640216222962910000103003830038300383003830038
1002430037224000061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000640216222962910000103003830038300383003830038
1002430037225000061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000670216222962910000103003830038300383003830038
10024300372240018061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000640216222962910000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sadalp v0.1d, v8.2s
  movi v1.16b, 0
  sadalp v1.1d, v8.2s
  movi v2.16b, 0
  sadalp v2.1d, v8.2s
  movi v3.16b, 0
  sadalp v3.1d, v8.2s
  movi v4.16b, 0
  sadalp v4.1d, v8.2s
  movi v5.16b, 0
  sadalp v5.1d, v8.2s
  movi v6.16b, 0
  sadalp v6.1d, v8.2s
  movi v7.16b, 0
  sadalp v7.1d, v8.2s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204200901500073925801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000000011110119016002006201600001002006620066200662006620066
160204200651500084125801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000000011110119016002006201600001002006620066200662006620066
16020420065150005025801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000000011110119016002006201600001002006620066200662006620066
160204200651500096925801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000280129011110119016002006201600001002006620066200662006620066
16020420065150002925801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000000011110119016002006201600001002006620066200662006620066
160204200651500074925801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000000011110119016002006201600001002006620066200662006620066
16020420065150001064258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100002300011110119016002006201600001002006620066200662006620066
1602042006515000114425801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000000011110119016002006201600001002006620066200662006620066
16020420065151002925801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000000011110119016002006201600001002006620066200662006620066
16020420065150009225801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000000011110119016002006201600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002420077150002862580010108000010800005064000011520027200462005032280010208000020160000200462005011160021109101016000010015310040821182021117172004315160000102004720047200472004720047
1600242004615000512580010108000010800005064000001520031200502005032280010208000020160000200462005011160021109101016000010000100308217204111772004315160000102004720047200492005320047
1600242004615000722580010108000010800005064000011520031200502004632280010208000020160000200462004611160021109101016000010000100401181182021117172004315160000102004720047200472004720047
1600242004615000108325800101080000108000050640000115200272004620046322800102080000201600002004620050111600211091010160000100001004082115204121772004315160000102004720047200472004720047
1600242005015000452580010108000010800005064000001520027200462004632280010208000020160000200462004611160021109101016000010012010040821172022117172004315160000102004720051200512005120047
16002420046150001079258001010800001080000506400001152002720046200463228001020800002016000020046200461116002110910101600001000331004382217242111772004315160000102005120047200512004720051
160024200461500045258001010801051080000506400001152003120152200503228001020800002016000020046200501116002110910101600001000010040112172421217172004330160000102005120047200472004720047
1600242011615000515258001010800001080000506400001152002720046200463228001020800002016000020050200461116002110910101600001002231003311217204111772004315160000102004720047200472004720047
16002420046150008792580010108000010800005064000011520027200462004632280010208000020160000200462004611160021109101016000010040100401121172021217172004315160000102004720047200472004720047
160024200461500010122580010108000010800005064000001520027200462004632280010208000020160000200462004611160021109101016000010025010040821172021117172004315160000102005120051200472004720047

Test 5: throughput

Count: 16

Code:

  sadalp v0.1d, v16.2s
  sadalp v1.1d, v16.2s
  sadalp v2.1d, v16.2s
  sadalp v3.1d, v16.2s
  sadalp v4.1d, v16.2s
  sadalp v5.1d, v16.2s
  sadalp v6.1d, v16.2s
  sadalp v7.1d, v16.2s
  sadalp v8.1d, v16.2s
  sadalp v9.1d, v16.2s
  sadalp v10.1d, v16.2s
  sadalp v11.1d, v16.2s
  sadalp v12.1d, v16.2s
  sadalp v13.1d, v16.2s
  sadalp v14.1d, v16.2s
  sadalp v15.1d, v16.2s
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

retire uop (01)cycle (02)03373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044007630002272516010810016000810016002050013201290400214004040040199776199911601202001600322003200644004940039111602011009910010016000010001111011801600400361600001004004140041400404004140041
1602044004829902412516010810016000910016002050013201320400214004940048199776199901601202001600322003200644004040039111602011009910010016000010001111011811601400371600001004004040041400404005040041
1602044004030003082516010810016001710016002050012801320400294003940039199776199901601202001604242003200644004940039111602011009910010016000010001111011811620400461600001004004140041400414004940040
16020440040300184312516010910016000910016002050013201310400204004940039199776199911601202001600322003200644004840039111602011009910010016000010001111011831620400371600001004004140041400414004040041
1602044004030003952516010910016001810016002050012801320400214004840039199776199911601202001600322003200644003940040111602011009910010016000010001111011821600400361600001004004940041400504005040041
16020440049300172652516010810016000810016002050012801320400204004940048199776199901601202001600322003200644004940048111602011009910010016000010001111011801600400451600001004005040049400404004940040
1602044003930002632516011710016001710016002050013201290400204004940039199776199901601202001600322003200644003940039111602011009910010016000010001111011811601400451600001004004140041400404004140040
1602044003930001362516010810016001710016002050012801320400204003940039199776199991601202001600322003200644004040040111602011009910010016000010001111011801610400361600001004004140040400494004040049
1602044003930002922516010910016000910016002050013201311400214004040049199776199911601202001600322003200644003940040111602011009910010016000010001111011821610400371600001004004940041400414004140049
16020440048300173012516011710016000910016002050012801320400204003940048199776199901601202001600322003200644003940049111602011009910010016000010001111011811600400461600001004004140040400504004040050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03l1i tlb fill (04)18191e373a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)accfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244005130000000073251600101016000010160000501280000010400294004840039199963200201600102016000020320000400394003911160021109101016000010000100241652032162221828400464113160000104004040040400914004040050
160024400393001000001842516001010160000101600005012800000110400204003940039199963200191600102016000020320000400394003911160021109101016000010000100251692117163225030400364115160000104004140049400404004040040
160024400393001000001172516001010160000101600005012800000110400204003940039199963200191600102016000020320000400394003911160021109101016000010000100251692123163223117400364113160000104010340049400494004940049
160024400393001000001002516001010160000101602435012800000110400204003940039199963200191600102016000020320000400394003911160021109101016000010000100271692129163222329400364114160000104004140040400404004040040
16002440048300100121715202516001010160000101600005012800000110400204003940039199963200191600102016000020320280400484003911160021109101016000010000100271692126163222228400364115160000104004940040400404004040040
160024400393001000004952516001010160000101600005023989990110400204003940039199963200281600102016000020320000400394003911160021109101016000010020100251692118163223019400364113160000104004040040400504004140040
160024400483001000002402516001010160000101600005023989990110400204004840039199963200191600102016000020320000400394003911160021109101016000010000100271692129163222931400364118160000104004040040400404004040040
16002440039299100000622516001010160000101600005012800000110400304003940039199963200191600102016000020320000400394003911160021109101016000010000100271692130163221830400364113160000104004040040400504004040040
160024400393001000001002516001010160000101600005012800000110400204003940039199963200191600102016000020320000400394003911160021109101016000010000100271692130163222330400364113160000104004040040400404004040040
160024400393001000001632516001010160000101600005012800000110400204003940039199963200191600102016000020320000400494003911160021109101016000010000100271692119163223019400364113160000104004040040400404004040040