Firestorm: SADALP (vector, 2D) measurements

Code:

  sadalp v0.2d, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	1	0	0	73	3	16	2	3	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	6	0	51	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	66	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	1	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  sadalp v0.2d, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	522	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28763	10421	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29693	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	103	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	82	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	24	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	1	45	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10485	20	20324	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	485	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	39	346	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	251	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  sadalp v0.2d, v0.4s

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	717	1	16	1	1	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	718	1	16	1	1	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	717	1	16	1	1	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	718	1	16	1	1	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	718	1	16	1	1	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	12	0	156	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10202	100	99	100	100	10000	100	0	1	1	1	718	1	16	1	1	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	232	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	717	1	16	1	1	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	717	1	16	1	1	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	718	1	17	1	1	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	717	1	16	1	1	29645	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	1	0	1	0	0	0	0	2	68	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	644	11	16	11	11	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	0	0	0	0	2	68	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	644	11	16	11	11	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	0	0	0	0	2	68	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	644	11	16	11	11	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	0	0	0	0	2	68	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	644	11	16	11	11	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	0	0	0	0	2	68	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28786	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	644	6	16	11	11	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	0	0	0	0	2	638	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	644	11	16	11	11	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	1	0	1	0	0	0	0	2	68	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	644	11	16	6	11	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	0	0	0	0	2	353	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	644	11	16	11	11	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	0	0	0	0	2	68	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	644	11	16	11	11	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	0	0	0	0	2	68	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	644	11	16	11	10	29629	0	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sadalp v0.2d, v8.4s
  movi v1.16b, 0
  sadalp v1.2d, v8.4s
  movi v2.16b, 0
  sadalp v2.2d, v8.4s
  movi v3.16b, 0
  sadalp v3.2d, v8.4s
  movi v4.16b, 0
  sadalp v4.2d, v8.4s
  movi v5.16b, 0
  sadalp v5.2d, v8.4s
  movi v6.16b, 0
  sadalp v6.2d, v8.4s
  movi v7.16b, 0
  sadalp v7.2d, v8.4s

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2509

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20078	150	0	0	39	29	25	80116	100	80016	100	80028	500	640196	1	1	5	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	2	0	0	1	1	1	10119	5	0	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	1	5	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	5	1	1	16	1	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	1	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	3	1	1	1	10120	5	0	0	16	1	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	1	5	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10120	5	1	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	1	5	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10120	5	0	1	16	1	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	159	29	25	80116	100	80016	100	80028	500	640196	1	1	5	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	5	0	2	16	1	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	1	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	5	1	0	16	0	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	1	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	5	1	0	16	0	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	12	29	25	80116	100	80016	100	80028	500	640196	0	1	5	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10120	5	1	1	16	1	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	1	5	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10120	5	1	1	16	1	0	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2507

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20091	150	1	1	1	0	0	45	27	80010	10	80000	10	80000	50	640000	1	1	0	20032	20051	20060	3	22	80010	20	80000	20	160000	20051	20060	1	1	160021	10	9	10	10	160000	10	0	10030	8	2	1	9	34	2	2	1	6	5	20048	20	1	160000	10	20061	20052	20061	20052	20061
160024	20051	150	0	0	0	0	60	51	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20060	20051	1	1	160021	10	9	10	10	160000	10	2	10028	8	4	1	3	25	2	1	1	4	5	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	0	6	51	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	10028	8	4	1	6	25	4	2	2	4	4	20048	40	1	160000	10	20052	20061	20061	20061	20052
160024	20060	150	0	0	0	0	0	51	29	80010	10	80000	10	80000	50	640000	1	1	5	20041	20060	20060	3	22	80010	20	80000	20	160000	20060	20051	1	1	160021	10	9	10	10	160000	10	0	10030	8	4	2	5	34	2	2	2	6	4	20048	40	2	160000	10	20052	20061	20061	20061	20061
160024	20060	150	0	0	0	0	0	51	29	80010	10	80000	10	80000	50	640000	0	1	5	20041	20060	20060	3	22	80010	20	80000	20	160000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	10031	11	5	2	3	34	4	2	2	3	5	20057	40	2	160000	10	20061	20061	20061	20052	20061
160024	20060	151	0	0	0	0	24	51	29	80010	10	80000	10	80000	50	640000	0	1	5	20041	20060	20060	3	22	80010	20	80000	20	160000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	10030	8	2	1	4	25	2	1	2	6	5	20057	20	2	160000	10	20052	20052	20061	20052	20061
160024	20051	151	0	0	1	0	18	51	29	80010	10	80000	10	80000	50	640000	0	1	5	20032	20060	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	10030	8	1	1	5	25	4	1	1	6	5	20048	20	2	160000	10	20052	20052	20061	20052	20061
160024	20051	150	0	0	0	0	0	45	27	80010	10	80000	10	80000	50	640000	0	1	5	20032	20060	20051	3	22	80010	20	80000	20	160000	20060	20051	1	1	160021	10	9	10	10	160000	10	0	10029	3	4	2	5	34	4	1	1	6	5	20048	40	2	160000	10	20061	20052	20061	20052	20061
160024	20051	150	0	0	0	0	0	51	29	80010	10	80000	10	80000	50	640000	0	1	5	20041	20060	20060	3	22	80010	20	80000	20	160000	20060	20129	1	1	160021	10	9	10	10	160000	10	0	10031	11	5	2	3	34	4	2	2	5	6	20057	40	2	160000	10	20061	20061	20061	20061	20061
160024	20060	150	0	0	1	0	0	51	29	80010	10	80000	10	80000	50	640000	0	1	5	20041	20060	20060	3	22	80010	20	80000	20	160000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	10030	8	2	1	3	25	2	2	2	5	4	20057	40	2	160000	10	20061	20061	20061	20061	20061

Test 5: throughput

Count: 16

Code:

  sadalp v0.2d, v16.4s
  sadalp v1.2d, v16.4s
  sadalp v2.2d, v16.4s
  sadalp v3.2d, v16.4s
  sadalp v4.2d, v16.4s
  sadalp v5.2d, v16.4s
  sadalp v6.2d, v16.4s
  sadalp v7.2d, v16.4s
  sadalp v8.2d, v16.4s
  sadalp v9.2d, v16.4s
  sadalp v10.2d, v16.4s
  sadalp v11.2d, v16.4s
  sadalp v12.2d, v16.4s
  sadalp v13.2d, v16.4s
  sadalp v14.2d, v16.4s
  sadalp v15.2d, v16.4s

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	1e	37	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40060	300	0	0	0	18	30	25	160117	100	160009	100	160020	500	2519300	40021	40049	40039	19977	6	19999	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40050	40040	40040	40050	40040
160204	40040	300	0	0	27	1	30	25	160108	100	160009	100	160020	500	1280132	40030	40039	40040	19977	6	19990	160120	200	160032	200	320064	40049	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40041	40050	40040	40050
160204	40039	300	0	0	0	0	30	25	160117	100	160009	100	160020	500	1280132	40030	40049	40039	19977	6	20000	160120	200	160032	200	320064	40040	40049	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40050	40040	40040	40050	40041
160204	40049	300	0	0	0	0	30	25	160109	100	160018	100	160020	500	1320132	40020	40040	40049	19977	6	20000	160120	200	160032	200	320064	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40050	40050	40050	40040	40050
160204	40039	300	0	0	0	0	333	25	160117	100	160017	100	160020	500	1320132	40030	40039	40040	19977	6	19990	160120	200	160032	200	320064	40049	40049	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40046	160000	100	40050	40040	40041	40050	40041
160204	40049	300	0	0	0	17	31	25	160117	100	160009	100	160020	500	1280132	40021	40049	40039	19977	6	19990	160120	200	160032	200	320064	40049	40049	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40037	160000	100	40049	40049	40040	40050	40050
160204	40039	300	0	0	0	18	30	25	160108	100	160009	100	160020	500	1280132	40030	40040	40040	19977	6	19991	160120	200	160032	200	320064	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40045	160000	100	40041	40041	40050	40040	40040
160204	40039	300	0	1	0	18	30	25	160108	100	160008	100	160178	500	2559102	40021	40049	40039	19977	6	20000	160120	200	160032	200	320064	40049	40049	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40037	160000	100	40050	40040	40041	40050	40041
160204	40049	300	0	0	0	18	30	25	160109	100	160008	100	160020	500	1320129	40021	40049	40039	19977	6	19991	160120	200	160032	200	320064	40040	40049	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40037	160000	100	40050	40050	40050	40050	40040
160204	40049	300	0	0	0	1	30	25	160118	100	160018	100	160020	500	1280132	40030	40039	40049	19977	6	19991	160120	200	160032	200	320064	40039	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40050	40040	40041	40050	40041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40051	300	1	0	0	0	0	0	0	0	1	58	0	25	160027	10	160000	10	160000	50	1345078	1	1	40020	40039	40049	19996	0	3	20019	160010	20	160000	20	320000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	3	1	1	7	16	2	1	1	12	10	40036	15	5	160000	10	40040	40052	40040	40040	40041
160024	40039	299	0	0	0	0	0	0	0	0	0	46	0	25	160010	10	160000	10	160000	50	1280000	1	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40051	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	3	1	1	10	16	2	1	1	12	12	40036	15	5	160000	10	40040	40052	40040	40052	40040
160024	40059	300	0	0	0	0	0	0	0	0	0	46	0	25	160010	10	160000	10	160000	50	1280000	1	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	96	0	10022	3	1	1	8	16	2	1	1	8	10	40036	15	5	160000	10	40040	40040	40040	40049	40040
160024	40085	300	0	0	0	1	0	0	0	0	0	46	0	25	160010	10	160000	10	160000	50	1280000	1	0	40020	40039	40039	19996	0	3	20019	160175	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	165	0	10022	3	1	1	11	16	2	1	1	10	7	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40052	300	0	0	0	0	0	0	0	0	0	718	0	25	160010	10	160000	10	160000	50	2398999	0	1	40032	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	183	0	10024	6	2	2	12	16	4	2	2	12	11	40036	30	10	160000	10	40040	40040	40040	40040	40052
160024	40060	299	0	0	0	0	0	0	0	0	0	46	0	25	160010	10	160000	10	160000	50	1280000	1	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	219	0	10022	3	1	1	12	16	2	1	1	12	12	40048	15	5	160000	10	40099	40050	40040	40040	40040
160024	40050	300	0	0	0	0	0	0	0	0	0	46	0	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40048	40049	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	186	0	10022	3	1	1	12	16	2	1	1	10	8	40036	15	5	160000	10	40040	40040	40050	40041	40040
160024	40050	300	0	0	0	0	0	0	0	0	0	46	0	25	160027	10	160000	10	160000	50	1280000	1	1	40029	40040	40039	19996	0	3	20019	160010	20	160000	20	320000	40051	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	3	1	1	13	16	2	1	1	10	8	40048	15	5	160000	10	40040	40052	40040	40040	40040
160024	40050	300	0	0	0	0	0	0	0	0	0	46	0	25	160027	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	3	1	1	8	16	2	1	1	11	12	40036	15	5	160000	10	40040	40052	40040	40040	40040
160024	40050	300	0	0	0	0	0	0	0	0	0	46	0	25	160010	10	160001	10	160000	50	1280000	1	1	40020	40039	40051	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	1	2	4600	6	10045	3	1	1	14	130	2	1	1	14	8	40480	15	5	160000	10	40545	40581	40355	40721	40643

SADALP (vector, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations