Firestorm: SADALP (vector, 2S) measurements

Code:

  sadalp v0.2s, v1.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	22	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	12	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	9	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	3	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	9	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	51	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  sadalp v0.2s, v1.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	2	2	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30085	224	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	6	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	91	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30084	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	224	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	9	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  sadalp v0.2s, v0.4h

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	1	1	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	0	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	1	16	1	1	29649	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	1	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	0	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	1	16	1	1	29649	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	1	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	0	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	718	1	16	1	1	29648	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	1	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	0	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	718	1	16	1	1	29648	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	1	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	0	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	1	16	1	1	29648	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	1	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	0	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	718	1	16	1	1	29648	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	1	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	0	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	1	16	1	1	29649	10000	100	30038	30038	30038	30038	30038
10204	30037	224	1	1	0	0	82	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	0	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	3	1	1	1	722	4	24	4	4	29629	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28252	0	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	722	4	24	4	4	29629	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28252	0	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	722	4	24	4	4	29629	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	224	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	40	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	447	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	444	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	510	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	393	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	402	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30064	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	429	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	456	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	381	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sadalp v0.2s, v8.4h
  movi v1.16b, 0
  sadalp v1.2s, v8.4h
  movi v2.16b, 0
  sadalp v2.2s, v8.4h
  movi v3.16b, 0
  sadalp v3.2s, v8.4h
  movi v4.16b, 0
  sadalp v4.2s, v8.4h
  movi v5.16b, 0
  sadalp v5.2s, v8.4h
  movi v6.16b, 0
  sadalp v6.2s, v8.4h
  movi v7.16b, 0
  sadalp v7.2s, v8.4h

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20089	150	3	956	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	201	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	72	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	21	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80133	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	18	504	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	18	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	444	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20080	150	1	204	0	45	27	80010	10	80000	10	80000	50	640000	1	0	0	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10043	3	5	2	19	25	2	1	1	20	9	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	15	0	45	27	80010	10	80000	10	80000	50	640000	1	0	10	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10043	3	1	1	19	25	2	1	1	19	9	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	45	27	80010	10	80000	10	80000	50	640000	0	0	0	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10040	13	1	1	19	25	2	1	1	8	19	20048	20	1	160000	10	20052	20134	20052	20052	20052
160024	20051	150	0	0	0	3701	27	80010	10	80000	10	80000	50	640000	1	0	0	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10043	3	9	2	19	34	4	2	2	9	16	20057	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	45	27	80010	10	80000	10	80000	50	640000	1	0	10	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10031	13	1	1	8	25	2	1	1	9	19	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	54	0	45	27	80010	10	80000	10	80000	50	640000	1	0	0	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10033	3	1	1	19	25	2	1	1	9	19	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	27	0	45	27	80010	10	80000	10	80000	50	640000	1	0	0	20041	20060	20060	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10031	13	1	2	9	25	2	1	1	9	19	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	21	0	45	27	80010	10	80000	10	80000	50	640000	1	0	0	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10033	19	1	1	7	34	2	1	1	19	9	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	21	0	45	27	80010	10	80000	10	80000	50	640000	1	0	0	20032	20051	20051	3	22	80010	20	80000	20	160268	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	10046	16	2	2	19	34	4	2	2	20	20	20057	40	2	160000	10	20061	20061	20061	20061	20061
160024	20060	150	0	75	0	45	27	80010	10	80000	10	80000	50	640000	1	0	10	20032	20051	20051	3	22	80010	20	80000	20	160000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	10043	13	2	2	19	34	4	2	2	7	19	20057	40	2	160000	10	20061	20061	20061	20061	20061

Test 5: throughput

Count: 16

Code:

  sadalp v0.2s, v16.4h
  sadalp v1.2s, v16.4h
  sadalp v2.2s, v16.4h
  sadalp v3.2s, v16.4h
  sadalp v4.2s, v16.4h
  sadalp v5.2s, v16.4h
  sadalp v6.2s, v16.4h
  sadalp v7.2s, v16.4h
  sadalp v8.2s, v16.4h
  sadalp v9.2s, v16.4h
  sadalp v10.2s, v16.4h
  sadalp v11.2s, v16.4h
  sadalp v12.2s, v16.4h
  sadalp v13.2s, v16.4h
  sadalp v14.2s, v16.4h
  sadalp v15.2s, v16.4h

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40059	300	21	17	31	25	160109	100	160008	100	160020	500	2399159	0	40029	40039	40039	19977	6	20000	160120	200	160032	200	320064	40039	40040	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40037	160000	100	40050	40040	40050	40050	40050
160204	40049	300	15	1	411	25	160108	100	160018	100	160020	500	2438997	0	40021	40049	40039	19977	6	20000	160120	200	160032	200	320064	40039	40040	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40037	160000	100	40040	40041	40050	40040	40041
160204	40040	300	39	0	837	25	160109	100	160008	100	160020	500	2399214	0	40020	40040	40039	19977	6	19991	160379	200	160032	200	320064	40039	40040	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40100	160000	100	40040	40049	40040	40040	40050
160204	40040	300	15	1	30	25	160108	100	160017	100	160020	500	2399159	0	40081	40039	40040	19977	6	19999	160120	200	160032	200	320064	40040	40049	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40052	160000	100	40040	40041	40041	40040	40040
160204	40049	300	39	17	30	25	160117	100	160009	100	160020	500	1320129	0	40029	40049	40040	19977	6	19990	160120	200	160032	200	320064	40048	40040	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40045	160000	100	40050	40050	40040	40040	40050
160204	40049	300	27	17	30	25	160118	100	160018	100	160020	500	2399159	0	40020	40039	40039	19977	6	20000	160120	200	160032	200	320064	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40046	160000	100	40040	40041	40040	40050	40050
160204	40039	300	24	0	31	25	160108	100	160008	100	160020	500	1280132	0	40030	40039	40039	19977	6	19990	160120	200	160032	200	320064	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40046	160000	100	40041	40041	40040	40050	40041
160204	40040	300	30	0	31	25	160108	100	160017	100	160020	500	1280132	0	40021	40049	40039	19977	6	19991	160120	200	160032	200	320064	40049	40048	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40045	160000	100	40040	40041	40041	40040	40041
160204	40039	300	36	1	40	25	160108	100	160008	100	160020	500	1320129	0	40029	40039	40040	19977	6	19999	160120	200	160032	200	320064	40049	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40037	160000	100	40040	40041	40050	40040	40050
160204	40049	300	36	17	31	25	160117	100	160008	100	160020	500	2438997	0	40021	40049	40040	19977	6	19990	160120	200	160032	200	320064	40048	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40041	40050	40040	40041	40041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	37	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40051	300	0	60	17	46	25	160010	10	160000	10	160000	50	2398999	1	1	5	40029	0	40048	40060	19996	3	20019	160010	20	160000	20	320000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	3	1	28	16	2	1	1	22	22	40037	20	6	160000	10	40049	40052	40049	40050	40049
160024	40048	300	0	24	17	55	25	160010	10	160000	10	160000	50	2398999	1	1	5	40020	0	40039	40047	19996	3	20019	160010	20	160000	20	320000	40039	40048	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	11	16	2	1	1	17	10	40046	20	6	160000	10	40049	40040	40040	40040	40040
160024	40039	300	0	24	0	55	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	0	40051	40046	19996	3	20020	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	17	16	2	1	1	17	17	40045	20	6	160000	10	40040	40049	40040	40049	40052
160024	40039	300	0	264	19	58	25	160029	10	160000	10	160000	50	1280000	1	1	5	40029	3	40048	40063	19996	3	20019	160010	20	160000	20	320844	40048	40051	1	1	160021	10	9	10	10	160000	10	0	0	10024	11	5	2	15	16	4	2	2	12	22	40048	40	18	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	24	0	55	25	160027	10	160000	10	160000	50	2398999	1	1	5	40029	0	40039	40044	19996	3	20028	160010	20	160000	20	320000	40048	40048	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	11	16	2	1	1	19	11	40045	20	6	160000	10	40040	40049	40040	40049	40040
160024	40039	300	0	27	0	46	25	160029	10	160000	10	160000	50	2398999	1	1	5	40029	0	40048	40073	19996	3	20031	160010	20	160000	20	320000	40051	40048	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	16	16	2	1	1	21	16	40036	20	6	160000	10	40052	40049	40040	40049	40040
160024	40039	300	0	24	17	55	25	160027	10	160017	10	160000	50	1280000	1	1	5	40029	0	40051	40047	19993	3	20019	160010	20	160000	20	320000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	16	16	2	1	1	11	16	40048	20	9	160000	10	40040	40049	40040	40040	40040
160024	40048	300	0	27	19	88	25	160010	10	160001	10	160000	50	2398999	1	1	5	40029	0	40039	40042	19996	3	20019	160010	20	160000	20	320000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	16	16	2	1	1	16	16	40045	20	6	160000	10	40052	40040	40040	40049	40052
160024	40039	299	0	30	0	46	25	160027	10	160001	10	160000	50	2678553	1	1	5	40020	0	40051	40057	19996	3	20019	160010	20	160000	20	320000	40039	40048	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	10	16	2	1	1	16	10	40045	20	6	160000	10	40040	40040	40049	40040	40050
160024	40048	299	0	33	17	625	25	160010	10	160000	10	160000	50	2678553	1	1	5	40020	0	40051	40042	19996	3	20028	160010	20	160000	20	320000	40051	40048	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	21	16	2	1	1	11	16	40036	20	9	160000	10	40049	40052	40049	40040	40049

SADALP (vector, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations