Firestorm: SADALP (vector, 4S) measurements

Code:

  sadalp v0.4s, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	9	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	57	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	63	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	18	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  sadalp v0.4s, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	224	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29539	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	2	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	2019	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	3	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10149	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	a9	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	2948	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	2	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	94	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  sadalp v0.4s, v0.8h

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	224	0	0	0	0	762	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28252	0	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28252	0	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	3	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28252	0	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28252	0	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28252	0	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28252	0	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	1	97	29547	25	10100	100	10007	100	10000	500	4277160	30018	0	30037	30037	28252	0	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28252	0	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28252	0	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28252	0	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	27	103	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	217	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	103	29547	44	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	18	329	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30084	225	0	324	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	84	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	535	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	560	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	369	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	1227	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sadalp v0.4s, v8.8h
  movi v1.16b, 0
  sadalp v1.4s, v8.8h
  movi v2.16b, 0
  sadalp v2.4s, v8.8h
  movi v3.16b, 0
  sadalp v3.4s, v8.8h
  movi v4.16b, 0
  sadalp v4.4s, v8.8h
  movi v5.16b, 0
  sadalp v5.4s, v8.8h
  movi v6.16b, 0
  sadalp v6.4s, v8.8h
  movi v7.16b, 0
  sadalp v7.4s, v8.8h

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20065	151	1	0	1	0	0	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	2	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	1	0	1	0	0	0	113	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20133	151	1	0	1	0	0	0	52	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20133	1	1	160201	100	99	100	100	160000	100	0	0	6	1	1	1	10119	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	1	0	1	0	0	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	0	3	1	1	1	10119	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	1	0	1	0	0	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	1	0	1	0	0	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	1	0	1	0	0	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	1	0	1	0	0	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	0	3	1	1	1	10119	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	1	0	1	0	0	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	0	3	1	1	1	10119	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	1	0	1	0	0	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20081	150	0	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10034	8	2	1	12	20	2	1	1	11	11	20043	15	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	87	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10032	8	2	1	9	20	2	1	1	12	11	20043	15	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	45	65	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10032	8	2	1	9	20	2	1	1	9	10	20043	15	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10034	8	2	1	9	20	2	1	1	8	9	20043	15	52	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	1	0	0	10032	8	2	1	9	20	2	1	1	9	9	20043	31	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	51	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10034	8	2	1	10	20	2	1	1	12	12	20043	15	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10033	8	2	1	11	20	2	1	1	9	12	20043	15	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10033	8	2	1	8	20	2	1	1	8	9	20043	15	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20052	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10032	8	2	1	9	24	4	1	1	9	9	20043	15	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	51	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10033	8	2	1	12	20	2	1	1	12	11	20043	30	0	160000	10	20047	20047	20047	20047	20047

Test 5: throughput

Count: 16

Code:

  sadalp v0.4s, v16.8h
  sadalp v1.4s, v16.8h
  sadalp v2.4s, v16.8h
  sadalp v3.4s, v16.8h
  sadalp v4.4s, v16.8h
  sadalp v5.4s, v16.8h
  sadalp v6.4s, v16.8h
  sadalp v7.4s, v16.8h
  sadalp v8.4s, v16.8h
  sadalp v9.4s, v16.8h
  sadalp v10.4s, v16.8h
  sadalp v11.4s, v16.8h
  sadalp v12.4s, v16.8h
  sadalp v13.4s, v16.8h
  sadalp v14.4s, v16.8h
  sadalp v15.4s, v16.8h

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	19	1f	37	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40085	299	1	0	0	0	96	25	160117	100	160017	100	160020	500	1320130	40020	0	40048	40040	19977	6	19991	160120	200	160032	200	320064	40039	40049	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	16	0	40037	160000	100	40050	40040	40041	40050	40049
160204	40040	300	0	0	0	17	30	25	160108	100	160008	100	160020	500	1320132	40021	0	40039	40039	19977	6	19990	160120	200	160032	200	320064	40040	40049	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	16	0	40046	160000	100	40040	40041	40050	40040	40040
160204	40048	300	0	0	0	0	40	25	160109	100	160008	100	160020	500	1320129	40021	0	40048	40039	19977	6	20000	160120	200	160032	200	320064	40049	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	16	0	40037	160000	100	40040	40050	40040	40041	40050
160204	40039	300	0	0	0	0	189	25	160108	100	160008	100	160020	500	1320131	40020	0	40039	40040	19977	15	20025	160120	200	160032	200	320064	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	16	0	40036	160000	100	40040	40041	40041	40040	40040
160204	40039	300	0	0	0	0	40	25	160108	100	160017	100	160020	500	1280132	40021	0	40040	40039	19977	6	20000	160120	200	160032	200	320064	40039	40049	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	16	0	40037	160000	100	40041	40050	40040	40041	40040
160204	40040	300	0	0	0	0	40	25	160108	100	160008	100	160020	500	1280132	40021	0	40040	40049	19977	6	20000	160120	200	160032	200	320064	40040	40049	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	16	0	40037	160000	100	40041	40050	40040	40041	40040
160204	40040	300	0	0	0	0	39	25	160117	100	160009	100	160020	500	2399159	40020	0	40040	40049	19977	6	19991	160120	200	160032	200	320064	40049	40039	1	1	160201	100	99	100	100	160000	100	6	0	1	1	1	10118	16	0	40036	160000	100	40041	40050	40040	40041	40040
160204	40040	300	0	0	0	1	93	25	160108	100	160017	100	160020	500	1280132	40030	0	40039	40039	19977	6	20000	160120	200	160032	200	320064	40048	40040	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	16	0	40045	160000	100	40040	40041	40050	40040	40041
160204	40040	300	0	0	0	0	30	25	160108	100	160009	100	160020	500	1280132	40030	0	40039	40040	19977	6	19991	160120	200	160032	200	320064	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	16	0	40037	160000	100	40040	40049	40041	40041	40041
160204	40040	300	0	0	0	0	39	25	160108	100	160009	100	160020	500	1280132	40021	0	40039	40039	19977	6	19991	160120	200	160032	200	320064	40039	40040	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	16	0	40046	160000	100	40049	40050	40040	40049	40041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40040	300	0	0	0	0	0	0	18	0	56	0	25	160011	10	160018	10	160000	50	1319997	1	1	5	40030	40049	40049	19996	0	3	20028	160010	20	160000	20	320000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	11	3	2	4	16	2	1	1	3	2	40046	15	6	160000	10	40050	40040	40328	40351	40452
160024	40525	304	1	1	8	9	1188	968	59	1	1521	4	171	161189	10	161106	10	161222	61	1736668	0	1	5	40367	40573	40494	20132	0	47	20317	161204	20	160981	20	322328	40629	40558	10	1	160021	10	9	10	10	160000	10	0	2	2	2	0	4033	0	10022	8	4	1	2	16	4	1	1	4	2	40046	15	6	160000	10	40050	40050	40050	40050	40040
160024	40049	300	0	0	0	0	51	0	18	0	89	0	25	160010	10	160001	10	160000	50	1280000	1	1	5	40029	40040	40040	19996	0	13	20078	160010	20	160000	20	320000	40049	40049	2	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	8	4	1	3	16	2	1	1	3	3	40036	15	5	160000	10	40049	40040	40040	40041	40040
160024	40040	300	0	0	3	0	0	0	18	0	184	0	25	160028	10	160017	10	160307	50	2438865	1	1	5	40030	40049	40039	19996	0	3	20028	160010	20	160000	20	320000	40049	40049	1	1	160021	10	9	10	10	160000	10	0	0	0	1	0	0	0	10022	11	5	1	2	16	2	1	1	3	2	40036	15	6	160000	10	40050	40050	40040	40050	40050
160024	40049	300	0	1	0	0	0	0	18	0	46	0	25	160467	10	160000	10	160000	50	2438865	1	1	5	40030	40048	40048	19996	0	3	20108	160010	20	160000	20	320000	40040	40048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10024	8	4	2	3	16	2	1	2	3	3	40045	15	5	160000	10	40041	40049	40040	40049	40102
160024	40039	300	0	0	0	0	0	0	18	0	56	0	25	160028	10	160018	10	160000	50	2399027	1	1	5	40030	40049	40049	19996	0	3	20146	160010	20	160000	20	320000	40049	40049	1	1	160021	10	9	10	10	160000	10	0	0	0	1	0	0	0	10022	8	4	1	2	16	2	1	1	2	3	40046	15	6	160000	10	40050	40050	40050	40040	40040
160024	40049	300	0	0	0	0	0	0	18	0	46	0	25	160028	10	160018	10	160000	50	2438865	1	1	5	40020	40049	40049	19996	0	8	20086	160010	20	160000	20	320000	40048	40099	2	1	160021	10	9	10	10	160000	10	0	0	0	1	2	0	0	10042	8	10	1	3	55	2	2	1	3	3	40046	15	6	160000	10	40050	40040	40050	40050	40040
160024	40049	300	0	0	0	0	12	0	18	0	55	0	25	160028	10	160113	10	160000	50	1280000	0	1	5	40020	40049	40049	19996	0	3	20019	160010	20	160000	20	320000	40049	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	8	4	1	2	16	2	1	1	3	3	40046	15	6	160000	10	40050	40050	40050	40040	40050
160024	40049	300	0	0	0	0	12	0	0	0	55	0	25	160011	10	160017	10	160000	50	2398999	1	1	5	40029	40040	40040	19996	0	3	20019	160010	20	160000	20	320000	40049	40049	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	3	0	10024	8	4	1	3	16	2	1	1	3	3	40046	15	6	160000	10	40050	40050	40049	40040	40049
160024	40049	299	0	0	0	0	0	0	18	0	56	0	25	160028	10	160000	10	160000	50	1280000	1	1	5	40029	40049	40049	19996	0	3	20019	160010	20	160000	20	320000	40049	40049	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	8	5	1	2	16	2	1	1	2	3	40046	15	6	160000	10	40050	40040	40100	40050	40050

SADALP (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations