Firestorm: SADALP (vector, 8H) measurements

Code:

  sadalp v0.8h, v1.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	22	0	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	88	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	103	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	1	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	9	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	3	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	12	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	1	3	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  sadalp v0.8h, v1.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	224	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	714	1	17	2	3	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28744	10125	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	4	3	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	714	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	25	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28744	10125	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	3	714	3	17	3	3	29634	25	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	1	0	0	103	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	204	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	4	4	2	12	710	1	16	1	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	103	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	3	710	1	17	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	4	0	0	0	0	0	640	2	16	2	2	29668	0	10000	10	30038	30038	30038	30085	30038
10024	30037	225	0	0	0	6	7	795	528	1	4489	29485	159	10063	13	10056	15	10894	77	4285455	0	30270	30323	30367	28294	31	28886	10906	20	10980	24	21980	30368	30355	7	1	10021	10	9	10	10	10000	10	0	0	1	2	19520	2	790	4	56	3	3	29897	2	10000	10	30366	30366	30419	30228	30321
10024	30409	227	0	0	1	7	7	927	616	0	3310	29476	179	10070	15	10040	11	11043	76	4286924	0	30270	30401	30366	28312	17	28900	11056	20	11151	21	22308	30358	30371	8	1	10021	10	9	10	10	10000	10	0	0	1	0	5338	2	795	4	97	2	2	29882	3	10000	10	30367	30368	30414	30405	30370
10024	30360	228	1	1	0	7	8	933	616	1	4564	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29701	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	9	0	0	61	29548	25	10010	10	10007	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  sadalp v0.8h, v0.16b

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28741	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	7	6	1	1	1	718	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	1	61	29547	25	10100	100	10000	100	10000	500	4279864	1	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30229	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	231	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	3	1	1	1	717	0	16	0	0	29646	0	10000	100	30086	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	4	0	0	0	0	1	1	1	717	0	37	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30085	225	0	0	0	0	0	0	5104	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	227	0	0	0	0	0	0	61	29547	25	10100	100	10008	100	10000	500	4277160	1	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28741	10100	200	10008	200	20358	30085	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	2	717	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30319	227	1	1	1	7	7	555	616	4489	29484	152	10066	11	10056	12	10600	61	4286624	1	30270	30408	30179	28313	0	34	28898	11060	20	10978	26	21946	30321	30322	2	1	10021	10	9	10	10	10000	10	2	0	1	4	19470	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	726	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	12	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sadalp v0.8h, v8.16b
  movi v1.16b, 0
  sadalp v1.8h, v8.16b
  movi v2.16b, 0
  sadalp v2.8h, v8.16b
  movi v3.16b, 0
  sadalp v3.8h, v8.16b
  movi v4.16b, 0
  sadalp v4.8h, v8.16b
  movi v5.16b, 0
  sadalp v5.8h, v8.16b
  movi v6.16b, 0
  sadalp v6.8h, v8.16b
  movi v7.16b, 0
  sadalp v7.8h, v8.16b

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20090	150	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	39	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	8	6	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	493	1	1	1	10119	0	71	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	27	436	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	159	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	9	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	4796	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	3	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	694	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	1	9	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	9	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20054	150	1	1	1	1	0	1	59	25	80010	10	80000	10	80000	50	640000	0	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20052	20048	1	1	160021	10	9	10	10	160000	10	9	10042	6	2	1	1	38	26	3	2	1	28	29	20049	16	160000	10	20049	20053	20053	20053	20053
160024	20052	150	1	1	1	2	0	1	108	25	80010	10	80000	10	80000	50	640000	0	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20048	20052	1	1	160021	10	9	10	10	160000	10	0	10057	6	2	2	1	28	26	3	2	1	29	30	20049	31	160000	10	20053	20049	20053	20049	20049
160024	20048	150	1	0	1	0	243	1	773	25	80010	10	80000	10	80000	50	640000	0	1	20029	20048	20048	3	22	80010	20	80000	20	160000	20048	20052	1	1	160021	10	9	10	10	160000	10	75	10053	6	2	2	2	29	28	3	2	2	23	30	20051	31	160000	10	20055	20055	20055	20049	20055
160024	20048	150	1	2	1	2	9	2	108	25	80010	10	80000	10	80000	50	640000	0	1	20035	20054	20054	3	22	80010	20	80000	20	160000	20054	20054	1	1	160021	10	9	10	10	160000	10	0	10056	6	2	1	1	29	26	1	2	2	31	28	20049	16	160000	10	20053	20053	20049	20053	20053
160024	20052	150	1	1	1	1	0	1	96	25	80010	10	80000	10	80000	50	640000	0	1	20029	20048	20052	3	22	80010	20	80000	20	160000	20052	20048	1	1	160021	10	9	10	10	160000	10	45	10050	6	2	2	1	26	22	1	2	1	21	25	20045	31	160000	10	20049	20049	20053	20049	20053
160024	20048	150	1	2	1	1	0	0	108	25	80010	10	80000	10	80000	50	640000	0	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	10053	6	2	2	1	26	26	3	2	1	21	25	20049	16	160000	10	20053	20053	20053	20049	20049
160024	20048	150	1	0	1	0	0	1	108	25	80010	10	80000	10	80000	50	640000	0	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	9	10048	6	1	1	1	23	26	1	1	2	15	25	20049	31	160000	10	20053	20053	20053	20053	20053
160024	20048	150	1	1	1	1	15	1	108	25	80010	10	80000	10	80000	50	640000	0	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20048	20048	1	1	160021	10	9	10	10	160000	10	6	10051	3	1	1	1	26	22	1	1	1	15	25	20045	16	160000	10	20049	20049	20053	20049	20049
160024	20048	150	1	1	1	1	0	0	132	25	80010	10	80000	10	80000	50	640000	1	1	20029	20048	20048	3	22	80010	20	80000	20	160000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	10051	3	1	1	1	24	22	1	1	1	18	28	20045	16	160000	10	20049	20049	20049	20053	20049
160024	20048	150	1	1	1	0	0	1	102	25	80010	10	80000	10	80000	50	640000	1	1	20029	20048	20048	3	22	80010	20	80000	20	160000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	10045	3	1	1	1	21	22	1	1	1	26	16	20045	16	160000	10	20049	20049	20049	20049	20049

Test 5: throughput

Count: 16

Code:

  sadalp v0.8h, v16.16b
  sadalp v1.8h, v16.16b
  sadalp v2.8h, v16.16b
  sadalp v3.8h, v16.16b
  sadalp v4.8h, v16.16b
  sadalp v5.8h, v16.16b
  sadalp v6.8h, v16.16b
  sadalp v7.8h, v16.16b
  sadalp v8.8h, v16.16b
  sadalp v9.8h, v16.16b
  sadalp v10.8h, v16.16b
  sadalp v11.8h, v16.16b
  sadalp v12.8h, v16.16b
  sadalp v13.8h, v16.16b
  sadalp v14.8h, v16.16b
  sadalp v15.8h, v16.16b

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40059	300	0	0	0	0	9	0	17	705	25	160108	100	160009	100	160020	500	1280132	40030	40039	40040	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10118	1	16	0	0	0	40036	0	160000	100	40050	40040	40050	40040	40041
160205	40039	299	0	0	0	0	0	0	0	31	25	160109	100	160017	100	160020	500	1320129	40020	40048	40039	19977	6	19990	160120	200	160032	200	320064	40049	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	156	0	1	1	1	10118	0	16	0	0	0	40036	0	160000	100	40041	40049	40040	40050	40050
160204	40039	300	0	0	0	0	0	0	0	39	25	160108	100	160017	100	160020	500	2439083	40020	40039	40049	19977	6	19990	160120	200	160032	200	320064	40049	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	141	0	1	1	1	10118	0	16	0	0	0	40046	0	160000	100	40049	40040	40040	40041	40050
160204	40048	300	0	0	0	0	0	0	0	31	25	160118	100	160008	100	160020	500	1280132	40030	40048	40048	19977	6	19991	160120	200	160032	200	320064	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	6	0	1	1	1	10118	0	16	1	0	0	40036	0	160000	100	40041	40041	40049	40049	40040
160204	40049	300	0	0	0	0	0	0	1	315	25	160109	100	160008	100	160020	500	2237497	40030	40039	40040	19977	6	19990	160120	200	160032	200	320064	40039	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	24	0	1	1	1	10118	0	16	0	0	0	40046	0	160000	100	40040	40041	40041	40041	40040
160204	40048	299	0	0	0	0	0	0	1	39	25	160108	100	160017	100	160020	500	1280132	40021	40040	40040	19977	6	19990	160120	200	160032	200	320064	40049	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	135	0	1	1	1	10118	0	16	0	0	0	40045	0	160000	100	40040	40040	40041	40050	40040
160204	40048	299	0	0	0	0	0	0	0	40	25	160108	100	160017	100	160020	500	1320129	40020	40049	40039	19977	6	19991	160120	200	160032	200	320064	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	165	0	1	1	1	10118	0	16	0	0	0	40037	0	160000	100	40041	40041	40050	40049	40040
160204	40040	299	0	0	0	0	0	0	0	30	25	160108	100	160017	100	160020	500	2399159	40029	40048	40048	19977	6	20000	160120	200	160032	200	320064	40048	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	147	0	1	1	1	10118	0	16	0	0	0	40046	0	160000	100	40041	40040	40041	40049	40040
160204	40039	299	0	0	0	0	0	0	0	40	25	160118	100	160017	100	160020	500	1280132	40030	40039	40049	19977	6	19991	160120	200	160032	200	320064	40040	40049	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	111	0	1	1	1	10118	0	16	0	0	0	40036	0	160000	100	40040	40041	40041	40040	40040
160204	40040	300	0	0	0	0	0	0	1	31	25	160117	100	160008	100	160020	500	2399159	40021	40048	40048	19977	6	19991	160120	200	160032	200	320064	40049	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	3	0	1	1	1	10118	0	16	0	0	0	40036	0	160000	100	40041	40050	40040	40041	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	37	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40058	300	0	0	0	46	43	160010	10	160000	10	160000	50	1280000	1	1	10	40029	40048	40039	19996	0	3	20019	160010	20	160107	20	320000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	0	10023	13	2	1	23	16	2	1	1	22	22	40036	15	5	160000	10	40049	40040	40049	40040	40049
160024	40039	300	0	0	1	46	25	160027	10	160017	10	160000	50	1280000	0	1	10	40020	40039	40048	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10023	13	5	1	21	16	2	1	1	8	21	40036	15	5	160000	10	40040	40040	40040	40049	40040
160024	40039	300	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	0	1	10	40020	40039	40048	19996	0	3	20028	160010	20	160000	20	320000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	0	10023	13	5	1	21	16	2	1	1	22	22	40036	15	5	160000	10	40040	40049	40040	40040	40049
160024	40039	300	144	88	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	10	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40048	1	1	160021	10	9	10	10	160000	10	0	0	10023	13	5	1	21	16	2	1	1	9	21	40045	15	5	160000	10	40040	40040	40040	40049	40040
160024	40039	300	0	0	17	46	25	160010	10	160000	10	160000	50	2398999	1	1	10	40020	40039	40048	19996	0	3	20028	160010	20	160000	20	320000	40039	40048	1	1	160021	10	9	10	10	160000	10	0	0	10023	13	5	1	9	16	2	1	1	21	7	40045	15	5	160000	10	40041	40049	40040	40040	40040
160024	40048	300	0	0	17	55	25	160010	10	160000	10	160000	50	1280000	1	1	10	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	0	10023	13	5	1	21	16	2	1	1	21	22	40036	15	5	160000	10	40040	40040	40049	40040	40040
160024	40039	300	0	0	17	46	25	160027	10	160000	10	160000	50	1280000	1	1	10	40020	40048	40039	19996	0	3	20019	160010	20	160000	20	320000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	0	10023	13	4	1	9	16	2	1	1	20	9	40048	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	46	25	160027	10	160000	10	160000	50	2398999	1	1	10	40029	40039	40039	19996	0	3	20028	160010	20	160000	20	320000	40052	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	13	4	1	6	16	2	1	1	21	10	40036	15	5	160000	10	40040	40040	40040	40040	40049
160024	40039	299	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	10	40020	40048	40039	19996	0	3	20029	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10023	13	4	1	9	16	2	1	1	20	21	40036	15	5	160000	10	40049	40049	40040	40040	40040
160024	40052	300	9	0	17	46	25	160010	10	160000	10	160000	50	1280000	1	1	10	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10023	13	4	1	20	16	2	1	1	20	22	40036	15	5	160000	10	40049	40041	40040	40040	40040

SADALP (vector, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations