Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SADDLP (vector, 1D)

Test 1: uops

Code:

  saddlp v0.1d, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715066168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203716061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203716061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  saddlp v0.1d, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0309181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500001241968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000821968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500002511968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000671011611197910100001002003820038200382003820038
1020420037150000611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000371011611197910100001002003820038200382003820038
1020420037150000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l1i tlb fill (04)l2 tlb miss data (0b)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371501000010319686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150001068419686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150000031215419686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150000006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037149000006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150000006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
10024200371500000017019686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150000006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150000006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150000006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  saddlp v0.1d, v8.2s
  saddlp v1.1d, v8.2s
  saddlp v2.1d, v8.2s
  saddlp v3.1d, v8.2s
  saddlp v4.1d, v8.2s
  saddlp v5.1d, v8.2s
  saddlp v6.1d, v8.2s
  saddlp v7.1d, v8.2s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)dde0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420049150000712580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000000001115118016020035800001002003920039200392003920039
8020420038150000292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000000001115118016020035800001002003920039200392014720039
8020420038151000292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000010001115171016020035800001002003920039200392003920039
80204200381500001782580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000000001115118016020035800001002003920039200392003920039
80204200381500004512580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000000001115118016020035800001002003920039200392003920039
8020420038150000292580108100800081008002050064013220019200382003899776998980120200800322008003220038200382180201100991001008000010000000001115118065020035800001002003920039200392003920039
80204200381500001152580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000000001115118016020035800001002003920039200392003920039
8020420038150000292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000000001115118016020035800001002003920039200392003920039
80204200381500002192580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000000001115118016020035800001002003920039200392003920039
8020420038150000292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000000001115118016020035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)09191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9accfd2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200511500000008725800101080000108000050640000200192003820038999631001880010208000020800002003820038118002110910108000010000005021001143114162003580000102003920039200392003920039
80024200381501100008725800101080000108000050640000200192003820038999631001880010208000020800002003820038118002110910108000010000005021001173117142003580000102003920039200392003920039
8002420038150110000872580010108000010800005064000020019200382003899963100188001020800002080000200382003811800211091010800001000000502000093012182003580000102003920039200392003920039
80024200381501100009925800101080000108000050640000200192003820038999631001880010208000020800002003820038118002110910108000010000047050210011429617172003580000102003920039200392003920039
8002420038150110000872580010108000010800005064000020019200862013799963100188001020800002080000200382003811800211091010800001000000502100117591882008180000102003920039200392003920039
80024200381501110132015025800101080000108000050640000200192003820038999631001880010208000020800002003820038118002110910108000010000035021001143017112003580000102003920039200392003920039
80024200381501100008725800101080000108000050640000200192003820038999631001880010208000020800002003820038118002110910108000010000005021001143017192003580000102003920039200392003920039
800242003815011000012925800101080000108000050640000200192003820038999631001880010208000020800002003820038118002110910108000010000005021001172914172003580000102003920039200392003920039
800242003815011000023625800101080000108000050640000200192003820038999631001880010208000020800002003820038118002110910108000010000005021001143017182003580000102003920039200392003920039
8002420038150110000872580010108000010800005064000020019200382003899963100188001020800002080000200382003811800211091010800001000000502100114301782003580000102003920039200392003920039