Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SADDLP (vector, 2S)

Test 1: uops

Code:

  saddlp v0.2s, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715061168625100010001000264521120182037203715713189510001000100020372037111001100044073116111786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715010316862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371606116862510001000100026452112018203720371571318951000100010002037203711100110004073116111786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  saddlp v0.2s, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150006119686251010010010000100100005002847521120018020037200371842131874510100200100002001000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521120018020037200371842131874510100200100002001000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521120018020037200371842131874510100200100002001000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521120018020037200371842131874510100200100002001000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
10204200371500015619686251010010010000100100005002847521120018020037200371842131874510100200100002001000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521120018020037200371842131874510100200100002001000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521120018020037200371842131874510100200100002001000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521120018020037200371842131874510100200100002001000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
1020420037150006119672251010010010000100100005002847521120018020037200371842131874510100200100002001000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475211200180200372003718421318745101002001000020010000200372003711102011009910010010000100011971021622197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150086019686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
10024200371500127219686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000140640216221978610000102003820038200382003820038
1002420037150020819686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
1002420037150053619686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  saddlp v0.2s, v8.4h
  saddlp v1.2s, v8.4h
  saddlp v2.2s, v8.4h
  saddlp v3.2s, v8.4h
  saddlp v4.2s, v8.4h
  saddlp v5.2s, v8.4h
  saddlp v6.2s, v8.4h
  saddlp v7.2s, v8.4h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)fetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006115000015925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000001115118216020035800001002003920039200392003920039
802042003815000013425801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000001115118016020035800001002003920039200392003920039
802042003815000029258010810080008100800205006401320200192003820038997769989801202008003220080032200382003811802011009910010080000100002201115118016020035800001002003920039200392003920039
802042003814900016125801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000001115118016020035800001002003920039200392003920039
80204200381500005025801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000001115118016020035800001002003920039200392003920039
802042003815000019725801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000101115118016020035800001002003920039200392003920039
8020420038150000197258010810080008100800205006401321200192010020038997712998980120200800322008003220098200381180201100991001008000010000201115118016020035800001002003920039200392003920039
802042003815000029258010810080104100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100002518731115118016020035800001002003920039200392003920039
802042003815001328889025801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000001115118016020035800001002003920039200392003920039
8020420038150000117125801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000101115118016020035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200511500000104258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000050203161120035080000102003920039200392003920039
80024200381500000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100460050201161120035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000050201161120035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000050201162220035080000102003920039200392003920039
8002420038150000045258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000050202162220035080000102003920039200392003920039
8002420038150000062258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000050202161120035080000102003920039200392003920039
80024200381500000104258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000050201161120035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000050201161120035080000102003920039200392003920039
80024200381500000508258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000050201161120035080000102003920039200392003920039
80024200381500000729258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010020050201161120035080000102003920039200392003920039