Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SADDLV (vector, 8B)

Test 1: uops

Code:

  saddlv h0, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723061254725100010001000398160130183037303724143289510001000200030373037111001100000073116112629100030383038303830383038
1004303722061254725100010001000398160030183037303724143289510001000200030373037111001100000073116112629100030383038303830383038
1004303722061254725100010001000398160030183037303724143289510001000200030373037111001100000073116112629100030383038303830383038
10043037221261254725100010001000398160030183037303724143289510001000200030373037111001100000073116112629100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000200030373037111001100000073116112629100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000200030373037111001100000073116112629100030383038303830383038
1004303722061254725100010001000398160030183037303724143289510001000200030373037111001100000073116112629100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000200030373037111001100000073116112629100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000200030373037111001100004973116112629100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000200030373037111001100000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  saddlv h0, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)030918191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000082295472510100100100001001000050042771601300183003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
102043003722500000726295472510100100100001001000050042771601300543003730037282643287601010020010000200200003003730037111020110099100100100001000047101161129633100001003003830038300383003830038
10204300372250000061295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
1020430037225100008412954725101001001000010010000500427716003001830037300372826432874510100200100002002000030037300371110201100991001001000010000147101161129633100001003003830038300383003830038
10204300372250000061295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
10204300372250000061295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
10204300372250000061295472510100100100001001000050042771601300183003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
10204300372250000061295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
10204300372250000061295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300853003830038
10204300372250000061295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500822954725100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722400612954725100101010000101000050427716003001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722500612954725100101010000101000050427716003001830037300372828682876710010201000020200003003730037111002110910101000010300640532222962910000103003830038300383003830038
100243003722500612954725100101010000101000050427716003001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722500612954725100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722500612954725100101010000101000050427716003001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722500612954725100101010000101000050427716003001830037300372828632876710010201000020200003003730037111002110910101000010000640216222985010000103003830038300383003830038
100243003722400822954725100101010000101000050427716003001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722500612954725100101010000101000050427716003001830037300372828632876710010201000020200003003730037111002110910101000010020640216222962910000103003830038300383003830038
100243003722500612954725100101010000101000050427716003001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  saddlv h0, v8.8b
  saddlv h1, v8.8b
  saddlv h2, v8.8b
  saddlv h3, v8.8b
  saddlv h4, v8.8b
  saddlv h5, v8.8b
  saddlv h6, v8.8b
  saddlv h7, v8.8b
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200391500030258010810080008100800205006401320200202003920039997769990801202008003220016006420039200391180201100991001008000010000111511801620036800001002004020040200402004020040
8020420039150231030258010810080008100800205006401320200202003920039997769990801202008003220016006420039200391180201100991001008000010000111511801620036800001002004020040200402004020040
80204200391500030258010810080008100800205006401320200202003920039997769990801202008003220016006420039200391180201100991001008000010000111511801620036800001002004020040200402004020040
802042003915030030258010810080008100800205006401320200202003920039997769990801202008003220016006420039200391180201100991001008000010000111511801620036800001002004020113200402010120040
80204200391500030258010810080008100800205006401320200202003920039997769990801202008003220016006420039200391180201100991001008000010000111511801620036800001002004020040200402004020040
80204200391503030258010810080008100800205006401320200202003920039997769990801202008003220016006420039200391180201100991001008000010000111511801620036800001002004020040200402004020040
80204200391500030258010810080008100800205006401320200202003920039997769990801202008003220016006420039200391180201100991001008000010013111511801620036800001002004020040200402004020040
80204200391500093258010810080008100800205006401320200202003920039997769990801202008003220016006420039200391180201100991001008000010000111511801620036800001002004020040200402004020040
80204200391500030258010810080008100800205006401320200202003920039997769990801202008003220016006420039200391180201100991001008000010000111511801620036800001002004020040200402004020040
80204200391500030258010810080008100800205006401320200202003920039997769990801202008003220016006420039200391180201100991001008000010003111511801620036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150008225800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000502001416152020036080000102004020040200402004020040
8002420039150004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000502001916181820036080000102004020040200402004020040
8002420039150004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000502001816181820036080000102004020040200402004020040
8002420039150004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000502001816181820036080000102004020040200402004020040
8002420039150004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000502002116182020036080000102004020040200402004020040
8002420039150147884025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000502002116201920036080000102004020040200402004020040
800242003915026404025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000502002016192020036080000102004020040200402004020040
8002420039150004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000502002016212020036080000102004020040200402004020040
80024200391501504025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100200502001916181920036080000102004020040200402004020040
8002420039150004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000502001816181820036080000102004020040200402004020040