Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SADDL (vector, 2D)

Test 1: uops

Code:

  saddl v0.2d, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037156116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037156116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037156116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037156116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037156116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037156116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037166116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037156116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037156116872510001000100026468002018203720371572318951000100020002037203711100110001073116111787100020382038203820382038
10042037156116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  saddl v0.2d, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101160119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150961196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150661196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101401119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001001470640216221978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100810640216221978510000102003820038200382003820038
100242003715000106119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715000006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715000006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500001514719687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715000006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010060640216221978510000102003820038200382003820038
100242003715000006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100930646216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  saddl v0.2d, v1.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010001657101161119791100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000847101161119791100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150008791968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006403162219785210000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100029006402162219785010000102003820038200382003820038
10024200371500010519687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100029006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
1002420037150001241968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010021006402162219785010000102003820038200382003820038
1002420037150003421968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
1002420037150002101968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
1002420037150001261968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
1002420037150101051968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  saddl v0.2d, v8.2s, v9.2s
  saddl v1.2d, v8.2s, v9.2s
  saddl v2.2d, v8.2s, v9.2s
  saddl v3.2d, v8.2s, v9.2s
  saddl v4.2d, v8.2s, v9.2s
  saddl v5.2d, v8.2s, v9.2s
  saddl v6.2d, v8.2s, v9.2s
  saddl v7.2d, v8.2s, v9.2s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420047150018725801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051103162120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500123825801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
802042003815064025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381504814525801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010002051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161220035800001002003920039200392003920039
802042003815004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392008820039
802042003815004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)l2 tlb miss data (0b)3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)dbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815000104258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000050204164432003580000102003920039200392003920039
80024200381500039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000050205163442003580000102003920039200392003920039
80024200381500039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000050204163442003580000102003920039200392003920039
80024200381500039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000050203164442003580000102003920039200392003920039
80024200381500039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000050204163342003580000102003920039200392003920039
80024200381500039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000050205163432003580000102003920039200392003920039
80024200381500060258001010800001080000506400000200192003820038999431001880010208000020160000200382003811800211091010800001000050204163452003580000102003920039200392003920039
80024200381560039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000050204163442003580000102003920039200392003920039
80024200381500039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000050204163442003580000102003920039200392003920039
80024200381500039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000050204163442003580000102003920039200392003920039