Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SADDL (vector, 8H)

Test 1: uops

Code:

  saddl v0.8h, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371561168725100010001000264680120182037203715723189510001000200020372037111001100000373116111787100020382038203820382038
100420371561168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371661168725100010001000264680120182037203715723189510001000200020372037111001100000373116111787100020382038203820382038
100420371561168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371661168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371661168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371561168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
10042037156116872510001000100026468012018203720371572318951000100020002037203711100110006022073116111787100020382038203820382038
100420371561168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371561168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  saddl v0.8h, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150006119687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010000070007101161119791100001002003820038200382003820038
1020420037150006119687431011810010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010000010007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010002010007101161119791100001002003820038201812003820038
1020420037150006119687251010010010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010000030007101161119791100001002003820038200382003820038
1020420037150008219687251010010010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010000000007351161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001012000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000640216421978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  saddl v0.8h, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)030f1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000007102162219791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000007102162219791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010003007102162219791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000007102162219791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000007412162219791100001002003820038200382003820038
102042003715003298196872510100100100001001000050028476802005420037200371842231874510100200100002002000020037200371110201100991001001000010000007102162219791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010010007102162219791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000007102162219791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000007102162219791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000007102165219791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500266196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001006448161881978510000102003820038200382003820038
1002420037150026619687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100644111612111978510000102003820038200382003820038
10024200371500266196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001006447168101978510000102003820038200852003820038
1002420037150926619687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100644111610101978510000102003820038200382003820038
1002420037150026619687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100644101610101978510000102003820038200382003820038
10024200371500273119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100644101610101978510000102003820038200382003820038
10024200371500266196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001006445161051978510000102003820038200382003820038
100242003715002661968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010064411161081978510000102003820038200382003820038
100242003715002661968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010064411161181978510000102003820038200382003820038
10024200371500254119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100644101612101978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  saddl v0.8h, v8.8b, v9.8b
  saddl v1.8h, v8.8b, v9.8b
  saddl v2.8h, v8.8b, v9.8b
  saddl v3.8h, v8.8b, v9.8b
  saddl v4.8h, v8.8b, v9.8b
  saddl v5.8h, v8.8b, v9.8b
  saddl v6.8h, v8.8b, v9.8b
  saddl v7.8h, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005815100078040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051105164320035800001002003920039200392003920039
80204200381500000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051103163420035800001002003920039200392003920039
80204200381500000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051104163420035800001002003920039200392003920039
80204200381500000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051103164320035800001002003920039200392003920039
80204200381500003040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051103164420035800001002003920039200392003920039
80204200381500000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051104164320035800001002003920039200392003920039
80204200381500000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051103164420035800001002003920039200392003920039
80204200381500000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051104164420035800001002003920039200392003920039
80204200381500000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051104164320035800001002003920039200392003920039
8020420038150000474040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051103163420035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000502001161120035180000102003920039200392003920039
800242003815003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000101468502001161120035080000102003920039200392003920039
8002420038150159392580010108000010800005064000002011820038200381000431001880010208000020160000200382003821800211091010800001000502003161120035080000102003920039200392003920039
80024200381500146258001010800001080000506400001200192003820038999661001880010208000020160000200382003811800211091010800001000502001162120035080000102003920039200392003920039
8002420038150039258010410800001280097506400001200192003820038999631001880010208000020160590200382003811800211091010800001000502001161120035080000102003920039200392003920039
8002420038150039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000502001161120035080000102003920039200392003920039
80024200381507539258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000502001161120035080000102003920039200392003920039
8002420038150255271258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001020502001161120035080000102003920039200392003920039
8002420038150039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000502001161120035080000102003920039200392003920039
80024200381502739258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000502001161120035080000102003920039200392003920039