Firestorm: SCVTF (scalar, fixed-point, D from W) measurements

Code:

  scvtf d0, w0, #3

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14112	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	3	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	379	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	3	73	1	16	1	1	373	1000	1000	378	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14165	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	112	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	12	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22837	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	380	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	380	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377

Test 2: Latency 1->2 roundtrip

Code:

  scvtf d0, w0, #3
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	977	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	1310	1	2	16	3	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	1310	1	3	16	3	3	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	973	0	0	0	0	0	0	130017	119406	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	1373	1	2	16	3	3	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	1310	1	3	16	3	3	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	3	0	1310	1	2	16	3	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	1310	1	3	16	3	2	129519	10000	10000	10000	10100	130033	130071	130033	130033	130033
30204	130032	973	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	1310	1	3	16	3	2	129573	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130036	974	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	1391	1	2	16	2	3	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	1310	1	3	16	3	3	129519	10000	10000	10000	10100	130033	130034	130036	130034	130033
30204	130032	974	0	0	0	12	0	0	130017	119409	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802822	0	130014	130035	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	1310	1	2	16	2	2	129520	10000	10000	10000	10100	130033	130033	130033	130034	130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130032	991	0	0	0	88	130019	119408	45	40010	10010	20000	10004	10	20000	10000	50	6214497	14800528	1	130164	130033	130033	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1329	2	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	1018	0	0	9	0	130017	119436	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	2	16	1	1	129519	10000	10000	10000	10010	130033	130068	130033	130033	130033
30024	130032	974	0	0	27	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130035	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	2	16	1	1	129579	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130025	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130033	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130033	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130035	130033	130033
30024	130032	974	0	0	3	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033

Test 3: throughput

Count: 8

Code:

  scvtf d0, w8, #3
  scvtf d1, w8, #3
  scvtf d2, w8, #3
  scvtf d3, w8, #3
  scvtf d4, w8, #3
  scvtf d5, w8, #3
  scvtf d6, w8, #3
  scvtf d7, w8, #3

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26711	200	0	0	0	0	0	0	26744	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	0	6	6664	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	0	0	0	0	26703	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	0	0	0	0	26716	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	16	0	26706	80000	80000	100	26714	26710	26710	26710	26710
160204	26709	200	0	0	0	0	0	0	26706	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	0	0	0	0	26695	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160205	26709	200	0	0	0	0	264	88	26925	128	94	160360	100	80260	80260	102	80396	80196	500	1179526	1898015	1	26989	26935	27051	6726	65	45	6814	160867	200	80407	80215	202	80407	80411	27039	26921	3	1	80201	100	99	100	100	80000	100	2	0	80000	0	0	2	1	1	1	5139	34	2	26994	80000	80000	100	26995	26930	26938	27061	27052
160204	26882	201	1	1	1	2	264	88	26700	0	25	160100	100	80000	80000	100	80020	80014	500	1169630	1888696	1	26690	26709	26714	6636	0	6	6662	160134	200	80020	80024	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	1	3	0	1	1	1	5117	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	0	0	0	0	26702	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	0	0	0	0	26704	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26714	200	0	0	26774	2	25	160010	10	80000	80000	10	80000	80000	50	1166222	1885276	1	26694	26714	26713	6654	3	6694	160010	20	80000	80000	20	80000	80000	26713	26712	1	1	80021	10	9	10	10	80000	10	80000	1	3	5020	0	6	16	5	4	26710	80000	80000	10	26724	26710	26714	26710	26714
160024	26713	201	12	0	26698	2	25	160010	10	80000	80000	10	80000	80000	50	1168400	1884318	1	26694	26713	26709	6656	3	6694	160010	20	80000	80000	20	80000	80000	26710	26713	1	1	80021	10	9	10	10	80000	10	80000	1	3	5020	0	5	16	5	5	26710	80000	80000	10	26725	26715	26710	26711	26711
160024	26713	200	0	0	26698	2	25	160010	10	80000	80000	10	80000	80000	50	1168827	1889126	1	26694	26709	26713	6656	3	6694	160010	20	80000	80000	20	80000	80000	26713	26709	1	1	80021	10	9	10	10	80000	10	80000	1	3	5020	0	5	16	6	3	26711	80000	80000	10	26715	26711	26715	26834	26715
160024	26710	200	12	0	26698	2	25	160010	10	80000	80000	10	80000	80000	50	1168104	1883899	1	26690	26714	26713	6653	3	6693	160010	20	80000	80000	20	80000	80000	26713	26713	1	1	80021	10	9	10	10	80000	10	80000	1	3	5020	0	3	16	3	5	26711	80000	80000	10	26729	26714	26714	26714	26714
160024	26713	200	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168643	1885424	1	26694	26709	26713	6657	3	6693	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	1	3	5020	0	3	16	6	3	26710	80000	80000	10	26719	26714	26714	26714	26710
160024	26713	200	12	0	26698	2	25	160010	10	80000	80000	10	80000	80000	50	1168066	1882550	1	26695	26709	26709	6657	3	6698	160010	20	80000	80000	20	80000	80000	26714	26713	1	1	80021	10	9	10	10	80000	10	80000	1	3	5020	0	3	16	4	6	26711	80000	80000	10	26726	26714	26714	26710	26714
160024	26709	200	0	0	26698	5	25	160010	10	80000	80000	10	80000	80000	50	1168234	1884032	1	26694	26713	26713	6653	3	6693	160010	20	80000	80000	20	80000	80000	26713	26713	1	1	80021	10	9	10	10	80000	10	80000	0	3	5020	0	4	16	6	3	26710	80000	80000	10	26710	26715	26714	26714	26715
160024	26713	200	12	0	26699	2	25	160010	10	80000	80000	10	80000	80000	50	1168351	1884032	1	26694	26713	26713	6656	3	6693	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	1	0	5020	0	3	16	3	6	26710	80000	80000	10	26714	26835	26713	26722	26714
160024	26713	200	12	0	26698	2	25	160010	10	80000	80000	10	80000	80000	50	1168715	1878510	1	26694	26713	26713	6657	3	6693	160010	20	80000	80000	20	80000	80000	26713	26713	1	1	80021	10	9	10	10	80000	10	80000	1	6	5020	0	5	16	6	5	26710	80000	80000	10	26730	26717	26714	26714	26714
160024	26709	200	0	0	26698	2	25	160010	10	80000	80000	10	80000	80000	50	1168463	1882009	1	26694	26714	26713	6653	3	6693	160010	20	80000	80000	20	80000	80000	26713	26709	1	1	80021	10	9	10	10	80000	10	80000	1	0	5020	0	6	16	6	6	26710	80000	80000	10	26719	26714	26714	26714	26714

SCVTF (scalar, fixed-point, D from W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations