Firestorm: SCVTF (scalar, fixed-point, D from X) measurements

Code:

  scvtf d0, x0, #3

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	3	0	365	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	380	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22869	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	1	0	73	1	16	1	1	373	1000	1000	377	377	379	377	377
2004	379	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	75	3	109	2000	1000	1000	1000	1000	376	377	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	73	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	376	1000	1000	377	377	377	377	377
2004	380	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	379	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	366	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	12	73	1	16	1	1	373	1000	1000	378	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	9	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	113	2000	1000	1000	1000	1000	379	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377

Test 2: Latency 1->2 roundtrip

Code:

  scvtf d0, x0, #3
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	974	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	1	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	0	130018	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130037	974	0	0	0	0	9	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	3	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	0	130017	119411	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130033	974	0	0	0	12	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126265	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	4	0	10000	1	3	0	1270	1	16	0	1	1	129595	10000	10000	10000	10010	130033	130033	130033	130036	130033
30024	130032	974	0	0	0	12	0	130017	119409	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	14	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	1270	2	16	0	1	1	129574	10000	10000	10000	10010	130033	130033	130033	130034	130033
30024	130032	974	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	3	0	1270	1	16	0	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	2	4	10003	0	0	0	1270	1	32	0	1	1	129522	10000	10000	10000	10010	130035	130033	130033	130034	130033
30024	130032	973	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	1270	1	16	0	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	973	0	0	0	69	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	1270	1	16	0	2	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126263	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	1270	1	16	0	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	1270	2	16	0	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	3	0	1270	1	16	0	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	1270	1	16	0	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033

Test 3: throughput

Count: 8

Code:

  scvtf d0, x8, #3
  scvtf d1, x8, #3
  scvtf d2, x8, #3
  scvtf d3, x8, #3
  scvtf d4, x8, #3
  scvtf d5, x8, #3
  scvtf d6, x8, #3
  scvtf d7, x8, #3

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26709	200	0	0	0	0	12	0	26694	2	25	160100	100	80000	80000	100	80020	80015	500	1170282	1882391	1	26690	26713	26713	6636	0	6	6662	160136	200	80024	80020	200	80024	80020	26722	26713	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	3	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26714	26714	26715	26714	26710
160204	26713	200	0	0	0	0	12	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26694	26709	26709	6636	0	6	6662	160136	200	80024	80020	200	80020	80020	26713	26713	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	1	3	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26715	26715	26710	26714	26710
160204	26713	200	0	0	0	0	12	0	26698	2	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884833	0	26694	26709	26713	6636	0	6	6658	160134	200	80024	80020	200	80024	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	1	3	0	1	1	1	5117	0	16	0	0	26710	80000	80000	100	26715	26714	26714	26710	26710
160204	26713	200	0	0	0	0	12	0	26698	0	25	160100	100	80000	80000	100	80020	80015	500	1175712	1881719	0	26694	26709	26713	6632	0	6	6658	160135	200	80020	80403	200	80020	80020	26719	26878	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	1	3	0	1	1	1	5117	0	16	0	0	26710	80000	80000	100	26714	26714	26710	26715	26714
160204	26709	200	0	0	0	0	12	0	26698	2	25	160100	100	80000	80000	100	80020	80015	500	1168299	1884163	1	26690	26709	26713	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26713	26713	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	1	3	0	1	1	1	5117	0	16	0	0	26710	80000	80000	100	26714	26710	26714	26710	26710
160204	26714	200	0	0	0	0	0	0	26698	2	25	160100	100	80000	80000	100	80020	80015	500	1168951	1881412	0	26690	26709	26713	6636	0	6	6658	160135	200	80024	80024	200	80020	80020	26709	26713	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	1	3	0	1	1	1	5117	0	16	0	0	26710	80000	80000	100	26714	26714	26710	26715	26714
160204	26713	200	0	0	0	0	12	0	26694	1	25	160100	100	80000	80000	100	80020	80014	500	1168951	1897784	0	26694	26713	26714	6632	0	6	6662	160136	200	80020	80020	200	80024	80020	26721	26709	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	1	1	1	5117	0	16	0	0	26710	80000	80000	100	26710	26715	26714	26714	26714
160204	26709	200	0	0	0	0	12	0	26698	0	25	160100	100	80000	80000	100	80020	80015	500	1177659	1884034	0	26694	26713	26709	6632	0	6	6658	160135	200	80024	80020	200	80020	80024	26710	26713	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	1	3	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26714	26710	26710	26714	26714
160204	26713	200	0	0	0	0	12	0	26694	3	25	160100	100	80000	80000	100	80020	80015	500	1175427	1878772	0	26690	26709	26713	6632	0	6	6658	160134	200	80595	80020	200	80020	80020	26715	26713	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	3	0	1	1	1	5117	0	16	0	0	26707	80000	80000	100	26714	26710	26714	26714	26710
160204	26709	200	0	0	0	0	0	0	26698	3	25	160100	100	80000	80000	100	80020	80015	500	1168540	1884215	0	26694	26714	26714	6632	0	6	6662	160135	200	80020	80020	200	80020	80020	26717	26709	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	1	0	0	1	1	1	5117	0	16	0	0	26710	80000	80000	100	26718	26724	26714	26724	26721

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26709	207	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26725	26768	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	0	0	0	6	16	3	2	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26802	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	0	0	0	2	16	2	2	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6655	3	6689	160010	20	80000	80000	20	80000	80000	26714	26709	2	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	0	0	0	2	16	6	3	26706	80000	80000	10	26901	26885	26714	26710	26710
160024	26709	200	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26718	26712	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	0	0	0	2	16	2	2	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26824	26711	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	0	0	0	6	16	2	2	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26715	26827	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	0	0	0	2	16	6	2	26716	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	26694	3	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	0	0	0	2	16	3	6	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	0	0	0	2	16	2	2	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	0	0	0	2	16	6	6	26708	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	0	0	0	6	16	6	6	26711	80000	80000	10	26710	26710	26714	26713	26710

SCVTF (scalar, fixed-point, D from X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations