Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SCVTF (scalar, fixed-point, H from H)

Test 1: uops

Code:

  scvtf h0, h0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723276125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303722309625472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303722126125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723516125472510001000100039816013018303730372414328951000100010003037303711100110001073116112629100030383038303830383038
10043037234810325472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303722426125472510001000100039816003018303730372414328951000100010003037303711100110001073116112629100030383038303830383038
1004303722276125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303722516125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723306125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303722456125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  scvtf h0, h0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250012103295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000101440710011611296330100001003003830038300383003830038
10204300372250012103295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000101680710111611296330100001003003830038300383003830038
10204300372250012103295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000101650710011611296330100001003003830038300383003830038
10204300372240001032954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010001030710011611296330100001003003830038300383003830038
1020430037224000103295472510100100100001001000050042771600300183003730084282683287451010020010000200100003003730037111020110099100100100001000101530710011611296330100001003003830038300383003830038
102043003722400121032954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000710011611296330100001003003830038300383003830038
102043003722500121032954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000030710011611296330100001003003830038300383003830038
1020430037233001241629547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100010180710011611296330100001003003830038300383003830038
10204300372250021612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010001030710011611296330100001003003830038300383003830038
1020430037225011261295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000001530710011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006403163329629010000103003830038300383003830038
1002430037225006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006403163329629010000103003830038300383003830038
1002430037225006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000101006403163329629010000103003830038300383003830038
1002430037225006129547251001010100001010000504277160030018300373008428291328767100102010000201000030037300371110021109101010000100006403163329629010000103003830038300383003830038
1002430037225006129547251001010100001010000504278512030018300373003728286328767100102010000201000030037300371110021109101010000100006403163329629010000103003830038300383003830038
1002430037225006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006403163329629010000103003830038300383003830038
1002430037225006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006403163329629010000103003830038300383003830038
1002430037225006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100006403163329629010000103003830038300383003830038
1002430037225006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006403163329629010000103003830038300383003830038
1002430037225006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006403163329629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  scvtf h0, h8, #3
  scvtf h1, h8, #3
  scvtf h2, h8, #3
  scvtf h3, h8, #3
  scvtf h4, h8, #3
  scvtf h5, h8, #3
  scvtf h6, h8, #3
  scvtf h7, h8, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581510012302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001003311151181160020036800001002004020040200402004020040
80204200391500012722580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001001011151180160020036800001002004020040200402004020040
802042003915000124522580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001001611151180160020036800001002004020040200402004020040
8020420039150000722580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000311151180160020036800001002004020040200402004020040
80204200391500012302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001001011151180160020036800001002004020040200402004020040
80204200391500012302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001001311151180160020036800001002004020040200402004020040
80204200391510012722580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001001311151180160020036800001002004020040200402004020040
80204200391500012722580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
80204200391500012302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001001611151180160020036800001002004020040200402004020040
802042003915000124102580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001001311151180160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)18191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acc2cfd0d2d5map dispatch bubble (d6)d9ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200711550001184162580010108000010800005064000000200202003920039999631001980010208000020080000200392003911800211091010800001072000502000151607122003680000102004020040200402004020040
8002420039150000004025800101080000108000050640000002002020039200399996310019800102080000200800002003920039118002110910108000010000005020511016012102003680000102004020040200402004020040
80024200391500000018742580010108000010800005064000000200202003920039999631001980010208000020080000200392003911800211091010800001000000502000516011112003680000102004020040200402004020040
800242003915000000402580010108000010800005064000000200202003920039999631001980010208000020080000200392003911800211091010800001000000502000916010102003680000102004020040200402004020040
80024200391500000040258001010800001080000506400000020020200392003999963100198001020800002008000020039200391180021109101080000100000050200061601172003680000102004020040200402004020040
8002420039150000004025800101080000108000050640000002002020039200399996310019800102080000200800002003920039118002110910108000010000005020001016010122003680000102004020040200402004020040
8002420039150000007052580010108000010800005064000000200202003920039999631001980010208000020080000200392003911800211091010800001000000502000141601172003680000102004020040200402004020040
8002420039150000004025800101080000108000050640000102002020039200399996310019800102080000200800002003920039118002110910108000010000159050200071607112003680000102004020040200402004020040
8002420039150000004025800101080000108000050640000102002020039200399996310019800102080000200800002003920039118002110910108000010000005020001016012122003680000102004020040200402004020040
8002420039150000004025800101080000108000050640000052002020039200399996310019800102080000200800002003920039118002110910108000010000005020001116013102003680000102004020040200402004020040