Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SCVTF (scalar, fixed-point, H from W)

Test 1: uops

Code:

  scvtf h0, w0, #3
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? simd retires (ee)f5f6f7f8fd
2004376363612520001000100010001000140752282013573763767231092000100010001000100037637611100110001000731161137310001000377377377377377
2004376303612520001000100010001000140752282013573763767231092000100010001000100037637611100110001000731161137310001000377377377377377
2004376303612520001000100010001000140752282013573763767231092000100010001000100037637611100110001000731161137310001000377377377377377
2004376303612520001000100010001000140752282013573763767231092000100010001000100037637611100110001000731161137610001000377377377377377
2004376303612520001000100010001000140752282013573763767231092000100010001000100037637711100110001000731161137310001000377377377377377
2004376303612520001000100010001000140752282013573763767231092000100010001000100037937611100110001000731161137310001000377377377377377
2004376303612520001000100010001000140752282013573763767231092000100010001000100037637611100110001000731161137310001000377377377377377
2004376303612520001000100010001000140752282013573763767231092000100010001000100037637611100110001000731161137310001000377377377377377
2004376303612520001000100010001000140752282003573763767231092000100010001000100037637611100110001000731161137310001000377377377377377
2004376303612520001000100010001000140752282013573763767231092000100010001000100037637611100110001000731161137310001000377377377377377

Test 2: Latency 1->2 roundtrip

Code:

  scvtf h0, w0, #3
  fmov x0, d0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

retire uop (01)cycle (02)03191e1f3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
3020413003297400013001911940825401001010020000100001002000010000500621454514802709130013130032130032125473712623630100200100032000520010003200051300341300321120201100991001010010000100100001021111131702161112953010000100001000010100130035130033130033130034130033
302041300339740180881300171194102540100101002000010000100200001000050062144971480270913001413003213003212545831262403010020010000200002001000020000130034130033112020110099100101001000010010000103000131012162212951910000100001000010100130033130033130034130036130036
3020413003297401201300191194082540100101002000010000100200001005050062144971480270913001313003213003212546631262443010020010000200002001000020000130034130035112020110099100101001000010010000103000131012162212951910000100001000010100130033130033130034130037130033
3020413003297401201300171194082540100101002000010000100200001000050062144971480270913001313003413003212546631262403010020010000200002001000020000130032130032112020110099100101001000010010000100000131012162312951910000100001000010100130033130033130033130033130033
3020413003297401201300171194082540100101002000010000100200001000050062145451480508213001613003213003212546631262403010020010000200002001000020000130032130032112020110099100101001000010010000103000131012162212951910000100001000010100130033130034130033130033130033
3020413003297301201300201194082540100101002000010000100200001000050062145931480270913001413003513003212546631262403010020010000200002001000020000130033130032112020110099100101001000010010000103000131012162212951910000100001000010100130033130033130033130033130033
302041300329740001300171194092540100101002000010000100200001000050062145451480282313001613003213003212546731262433010020010000200002001000020000130032130032112020110099100101001000010010000003000131012162212952010000100001000010100130033130033130033130036130034
3020413003297401201300171194082540100101002000010000100200001000050062146411480270913001313003213003212546631262403010020010000200002001000020000130032130032112020110099100101001000010010000103001131012162212952110000100001000010100130033130033130033130033130033
302041300329740001300171194082540100101002000010000100200001000050062145451481005913001313003213003212546631262403010020010000200002001000020000130032130033112020110099100101001000010010000100000131012162212951910000100001000010100130033130034130033130033130033
3020413003397401201300171194082540100101002000010000100200001000050062144971480282113001313003513003212546631262403010020010000200002001000020000130032130032112020110099100101001000010010000103000131012162212957310000100001000010100130033130036130034130033130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
3002413003297500000120013001711944625400101001020000100001020113101968362620291493656501303850130034130034125492312626230010201055221466201024321222131026130949112002110910100101000010210059017111501772427303213146510043100001000010010132303132387132565132046132410
30024132454989100302439932552113245812049863640204100532007210060132268211421556269301149617700132150013210613242012654319012776234816241214723400261207523523132869132621351200211091010010100001041005511271030127011601112951910000100001000010010130035130033130033130033130033
3002413003297400000120013002011940925400101001020000100001020000100005062144971480052801300130130032130032125567312626230176201000020000201000020000130032130034112002110910100101000010010000130127011601112951910002100001000010010130033130035130034130033130036
3002413003297400100420013001711948125400191001120006100021020000100005062144971480064101300130130032130035125552312626230010201000020000201000020000130032130034112002110910100101000010010000030127011601112951910000100001000010010130033130034130033130033130033
3002413003297400000360013001711940825400101001020000100001020000100005062145451480097801300130130032130032125489312626230010201000020000201000020000130032130032112002110910100101000010010000030127011601112951910000100001000010010130088130034130033130036130033
300241300329740000000013001711940925400101001020000100001020000100005062144971480052801300150130032130033125489312626230010201000020000201000020000130032130032112002110910100101000010010000130127011601112951910000100001000010010130033130034130036130034130033
3002413013197400000120013001711941025400101001020000100001020000100005062145451480064111300130130041130034125489312626330010201000020000201000020000130032130035112002110910100101000010010000330127021611112951910000100001000010010130034130035130033130033130033
3002413003297400000120013001711940825400101001020000100001020000100005062144971480052801300140130032130032125489312626230177201000020000201000020000130032130032112002110910100101000010010000000127011601112951910000100001000010010130033130034130034130033130033
3002413003297400000450013001711940825400101001020000100001020000100005062144971480052801300130130032130033125489312626230010201000020000201000020000130032130032112002110910100101000010010000800127011601112951910000100001000010010130033130033130040130033130034
3002413003297400000120013001711940825400101001020000100001020000100005062144971480075601300130130032130032125489312626230010201000020000201000020000130032130032112002110910100101000010010000130127011601112951910000100001000010010130033130034130033130033130033

Test 3: throughput

Count: 8

Code:

  scvtf h0, w8, #3
  scvtf h1, w8, #3
  scvtf h2, w8, #3
  scvtf h3, w8, #3
  scvtf h4, w8, #3
  scvtf h5, w8, #3
  scvtf h6, w8, #3
  scvtf h7, w8, #3
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

retire uop (01)cycle (02)031e3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)dde0? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042671220002670902516010010080000800001008002080015500116895118841631266902670926709663225680316013620080020800202008002080020267092670911802011009910010080000100800000011151171602670680000800001002671026710267102671026710
160204267092000267010251601001008000080000100800208001550011689511884163126690267092670966326665816013520080020800202008002080020267092670911802011009910010080000100800000011151171602670680000800001002671026710267102671026710
160204267092000267040251601001008000080000100800208001550011689511884163126690267092670966326665816013520080020800202008002080020267112670921802011009910010080000100800000011151171602670680000800001002671026710267102671026710
160204267092000266980251601001008000080000100800208001550011689511884163126690267092670966326665816013520080020800202008002080020267102670911802011009910010080000100800000011151171602670680000800001002671026710267102671026710
160204267092000269160251601001008000080000100800208001550011689511884163126690267092670966326665816013520080020800202008002080020267092670911802011009910010080000100800000011151171602670680000800001002671026710267102671026710
1602042670920002695902516010010080000800001008002080015500116895118841631266902670926709663243666916014120080020800202008002080020267092670911802011009910010080000100800000011151171602670680000800001002671026710267102671026710
160204267092000267050251601001008000080000100800208001550011689511884163126690267092670966566665816013520080020800202008002080020267092670911802011009910010080000100800000011151171602670680000800001002671026710267102671026710
160204267092000267000251601001008000080000100800208001550011689511884163126690267092670966326665816013520080020800202008002080020267092670911802011009910010080000100800000011151171602670680000800001002671026710267102671026710
160204267092000267070251601001008000080000100800208001550011689511884163126690267092671166326665816013520080020800202008002080020267092670911802011009910010080000100800000011151171602670680000800001002671026710267102671026710
160204267092000266940251601001008000080000100800208001550011689511884163126690267092670966326665816013520080020800202008002080020267092670911802011009910010080000100800001011151171602670680000800001002671026710267102671026710

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

retire uop (01)cycle (02)031e3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600242688121712267012251600101080000800001080000800005011719211884032102669026709267136657366931600102080000800002080000800002671426713118002110910108000010800000050200018162314267118000080000102671426714267102671426710
160024267132000267070251600101080000800001080000800005011688801884032002669426714267096657366931600102080000800002080000800002671326714118002110910108000010800000350200023161623267108000080000102671426714267142671426714
1600242671320012267080251600101080000800001080000800005011744791884013002669026709267146653366931600102080000800002080000800002671326710118002110910108000010800001350200018162217267108000080000102671026714267142671426714
1600242671420012267282251600101080000800001080000800005011689401884015102669426713267136657366931600102080000800002080000800002671526713118002110910108000010800000350200022162323267068000080000102671026714267142671426710
1600242670920012267073251600101080000800001080000800005011681531882520102669026714267096653366901600102080000800002080000800002690426726118002110910108000010800001050200022162223267068000080000102671026711267142671426710
1600242671319912267223251600101080000800001080000800005011682581884727102669426713267126657366931600102080000800002080000800002671326713118002110910108000010800000350200023161422267068000080000102671426714267172671726714
1600242671420012267243251600101080000800001080000800005011681021884032102669426709267136653366891600102080000800002080000800002670926714118002110910108000010800001050200017162217267068000080000102671026714267102671426714
1600242671320012267102251600101080000800001080000800005011816181887607102669426709267096656366931600102080000800002080000800002670926709118002110910108000010800001350860023161722267228000080000102671426714267142671026710
1600242671320012267032251600101080000800001080000800005011686341883468102669426713267146656366891600102080000800002080000800002670926709118002110910108000010800000350200022162323267068000080000102671026710267142671526714
160024267092000267060251600101080000800001080000800005011695331884568102669426714267136657366931600102080000801922080000800002672726713118002110910108000010800001050430013162218267108000080000102671427306267182671526715