Firestorm: SCVTF (scalar, fixed-point, H from W) measurements

Code:

  scvtf h0, w0, #3

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	3	6	361	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	73	1	16	1	1	376	1000	1000	377	377	377	377	377
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	377	1	1	1001	1000	1000	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	379	376	1	1	1001	1000	1000	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	73	1	16	1	1	373	1000	1000	377	377	377	377	377

Test 2: Latency 1->2 roundtrip

Code:

  scvtf h0, w0, #3
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	974	0	0	0	130019	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214545	14802709	130013	130032	130032	125473	7	126236	30100	200	10003	20005	200	10003	20005	130034	130032	1	1	20201	100	99	100	10100	10000	100	10000	1	0	21	1	1	1	1317	0	2	16	1	1	129530	10000	10000	10000	10100	130035	130033	130033	130034	130033
30204	130033	974	0	180	88	130017	119410	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	130014	130032	130032	125458	3	126240	30100	200	10000	20000	200	10000	20000	130034	130033	1	1	20201	100	99	100	10100	10000	100	10000	1	0	3	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130034	130036	130036
30204	130032	974	0	12	0	130019	119408	25	40100	10100	20000	10000	100	20000	10050	500	6214497	14802709	130013	130032	130032	125466	3	126244	30100	200	10000	20000	200	10000	20000	130034	130035	1	1	20201	100	99	100	10100	10000	100	10000	1	0	3	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130034	130037	130033
30204	130032	974	0	12	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	130013	130034	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	1	0	0	0	0	0	1310	1	2	16	2	3	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	12	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214545	14805082	130016	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	1	0	3	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130034	130033	130033	130033
30204	130032	973	0	12	0	130020	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214593	14802709	130014	130035	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130033	130032	1	1	20201	100	99	100	10100	10000	100	10000	1	0	3	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	130017	119409	25	40100	10100	20000	10000	100	20000	10000	500	6214545	14802823	130016	130032	130032	125467	3	126243	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	3	0	0	0	1310	1	2	16	2	2	129520	10000	10000	10000	10100	130033	130033	130033	130036	130034
30204	130032	974	0	12	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214641	14802709	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	1	0	3	0	0	1	1310	1	2	16	2	2	129521	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214545	14810059	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130033	1	1	20201	100	99	100	10100	10000	100	10000	1	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130034	130033	130033	130033
30204	130033	974	0	12	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802821	130013	130035	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	1	0	3	0	0	0	1310	1	2	16	2	2	129573	10000	10000	10000	10100	130033	130036	130034	130033	130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130032	975	0	0	0	0	0	12	0	0	130017	119446	25	40010	10010	20000	10000	10	20113	10196	83	6262029	14936565	0	130385	0	130034	130034	125492	3	126262	30010	20	10552	21466	20	10243	21222	131026	130949	1	1	20021	10	9	10	10010	10000	10	2	10059	0	171115	0	1772	4	273	0	3	2	131465	10043	10000	10000	10010	132303	132387	132565	132046	132410
30024	132454	989	1	0	0	30	24	3993	2552	1	132458	120498	636	40204	10053	20072	10060	13	22682	11421	55	6269301	14961770	0	132150	0	132106	132420	126543	190	127762	34816	24	12147	23400	26	12075	23523	132869	132621	35	1	20021	10	9	10	10010	10000	10	4	10055	1	127103	0	1270	1	16	0	1	1	129519	10000	10000	10000	10010	130035	130033	130033	130033	130033
30024	130032	974	0	0	0	0	0	12	0	0	130020	119409	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	0	130032	130032	125567	3	126262	30176	20	10000	20000	20	10000	20000	130032	130034	1	1	20021	10	9	10	10010	10000	10	0	10000	1	3	0	1270	1	16	0	1	1	129519	10002	10000	10000	10010	130033	130035	130034	130033	130036
30024	130032	974	0	0	1	0	0	42	0	0	130017	119481	25	40019	10011	20006	10002	10	20000	10000	50	6214497	14800641	0	130013	0	130032	130035	125552	3	126262	30010	20	10000	20000	20	10000	20000	130032	130034	1	1	20021	10	9	10	10010	10000	10	0	10000	0	3	0	1270	1	16	0	1	1	129519	10000	10000	10000	10010	130033	130034	130033	130033	130033
30024	130032	974	0	0	0	0	0	36	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214545	14800978	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	3	0	1270	1	16	0	1	1	129519	10000	10000	10000	10010	130088	130034	130033	130036	130033
30024	130032	974	0	0	0	0	0	0	0	0	130017	119409	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130015	0	130032	130033	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	1	3	0	1270	1	16	0	1	1	129519	10000	10000	10000	10010	130033	130034	130036	130034	130033
30024	130131	974	0	0	0	0	0	12	0	0	130017	119410	25	40010	10010	20000	10000	10	20000	10000	50	6214545	14800641	1	130013	0	130041	130034	125489	3	126263	30010	20	10000	20000	20	10000	20000	130032	130035	1	1	20021	10	9	10	10010	10000	10	0	10000	3	3	0	1270	2	16	1	1	1	129519	10000	10000	10000	10010	130034	130035	130033	130033	130033
30024	130032	974	0	0	0	0	0	12	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130014	0	130032	130032	125489	3	126262	30177	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	1	16	0	1	1	129519	10000	10000	10000	10010	130033	130034	130034	130033	130033
30024	130032	974	0	0	0	0	0	45	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	0	130032	130033	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	8	0	0	1270	1	16	0	1	1	129519	10000	10000	10000	10010	130033	130033	130040	130033	130034
30024	130032	974	0	0	0	0	0	12	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800756	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	1	3	0	1270	1	16	0	1	1	129519	10000	10000	10000	10010	130033	130034	130033	130033	130033

Test 3: throughput

Count: 8

Code:

  scvtf h0, w8, #3
  scvtf h1, w8, #3
  scvtf h2, w8, #3
  scvtf h3, w8, #3
  scvtf h4, w8, #3
  scvtf h5, w8, #3
  scvtf h6, w8, #3
  scvtf h7, w8, #3

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26712	200	0	26709	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	25	6803	160136	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	26701	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	26704	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26711	26709	2	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	26698	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26710	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	26916	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	26959	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	43	6669	160141	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	26705	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6656	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	26700	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	26707	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26711	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	1	0	1	1	1	5117	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26881	217	12	26701	2	25	160010	10	80000	80000	10	80000	80000	50	1171921	1884032	1	0	26690	26709	26713	6657	3	6693	160010	20	80000	80000	20	80000	80000	26714	26713	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	0	0	18	16	23	14	26711	80000	80000	10	26714	26714	26710	26714	26710
160024	26713	200	0	26707	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26694	26714	26709	6657	3	6693	160010	20	80000	80000	20	80000	80000	26713	26714	1	1	80021	10	9	10	10	80000	10	80000	0	3	5020	0	0	23	16	16	23	26710	80000	80000	10	26714	26714	26714	26714	26714
160024	26713	200	12	26708	0	25	160010	10	80000	80000	10	80000	80000	50	1174479	1884013	0	0	26690	26709	26714	6653	3	6693	160010	20	80000	80000	20	80000	80000	26713	26710	1	1	80021	10	9	10	10	80000	10	80000	1	3	5020	0	0	18	16	22	17	26710	80000	80000	10	26710	26714	26714	26714	26714
160024	26714	200	12	26728	2	25	160010	10	80000	80000	10	80000	80000	50	1168940	1884015	1	0	26694	26713	26713	6657	3	6693	160010	20	80000	80000	20	80000	80000	26715	26713	1	1	80021	10	9	10	10	80000	10	80000	0	3	5020	0	0	22	16	23	23	26706	80000	80000	10	26710	26714	26714	26714	26710
160024	26709	200	12	26707	3	25	160010	10	80000	80000	10	80000	80000	50	1168153	1882520	1	0	26690	26714	26709	6653	3	6690	160010	20	80000	80000	20	80000	80000	26904	26726	1	1	80021	10	9	10	10	80000	10	80000	1	0	5020	0	0	22	16	22	23	26706	80000	80000	10	26710	26711	26714	26714	26710
160024	26713	199	12	26722	3	25	160010	10	80000	80000	10	80000	80000	50	1168258	1884727	1	0	26694	26713	26712	6657	3	6693	160010	20	80000	80000	20	80000	80000	26713	26713	1	1	80021	10	9	10	10	80000	10	80000	0	3	5020	0	0	23	16	14	22	26706	80000	80000	10	26714	26714	26717	26717	26714
160024	26714	200	12	26724	3	25	160010	10	80000	80000	10	80000	80000	50	1168102	1884032	1	0	26694	26709	26713	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26714	1	1	80021	10	9	10	10	80000	10	80000	1	0	5020	0	0	17	16	22	17	26706	80000	80000	10	26710	26714	26710	26714	26714
160024	26713	200	12	26710	2	25	160010	10	80000	80000	10	80000	80000	50	1181618	1887607	1	0	26694	26709	26709	6656	3	6693	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	1	3	5086	0	0	23	16	17	22	26722	80000	80000	10	26714	26714	26714	26710	26710
160024	26713	200	12	26703	2	25	160010	10	80000	80000	10	80000	80000	50	1168634	1883468	1	0	26694	26713	26714	6656	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	3	5020	0	0	22	16	23	23	26706	80000	80000	10	26710	26710	26714	26715	26714
160024	26709	200	0	26706	0	25	160010	10	80000	80000	10	80000	80000	50	1169533	1884568	1	0	26694	26714	26713	6657	3	6693	160010	20	80000	80192	20	80000	80000	26727	26713	1	1	80021	10	9	10	10	80000	10	80000	1	0	5043	0	0	13	16	22	18	26710	80000	80000	10	26714	27306	26718	26715	26715

SCVTF (scalar, fixed-point, H from W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations