Firestorm: SCVTF (scalar, fixed-point, H from X) measurements

Code:

  scvtf h0, x0, #3

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	1	0	73	3	16	2	2	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	2	16	2	2	373	1000	1000	377	379	377	377	377
2004	376	2	0	365	0	25	2000	1000	1000	1000	1000	14075	22911	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	377	1	1	1001	1000	1000	0	0	73	2	16	2	2	373	1000	1000	377	379	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	2	16	2	2	374	1000	1000	377	377	377	380	379
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	2	0	73	2	16	2	2	373	1000	1000	377	377	377	377	382
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	2	16	2	2	373	1000	1000	377	378	377	377	384

Test 2: Latency 1->2 roundtrip

Code:

  scvtf h0, x0, #3
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	974	0	0	0	0	0	0	130017	119607	25	40100	10100	20000	10000	100	20000	10049	500	6214497	14802709	1	130013	0	130032	130033	125466	3	126240	30429	204	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	3	0	0	1330	1	2	16	2	2	129524	10000	10000	10000	10100	130033	130033	130036	130033	130033
30204	131899	994	0	1	0	1	0	0	130017	119556	112	40179	10117	20003	10000	124	20000	10000	500	6216882	14802709	0	130013	0	131109	130349	125466	9	126556	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	2	2	10000	0	0	16793	0	0	1366	1	2	67	2	3	129523	10027	10000	10000	10100	130033	130128	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119411	25	40100	10100	20000	10000	100	20000	10000	500	6216632	14807957	0	130013	0	130365	130033	125466	3	126240	30100	212	10000	20488	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	1	0	10000	0	0	6	0	0	1310	1	2	16	2	2	129599	10000	10000	10000	10100	130582	130033	130033	130033	130033
30204	130032	974	0	0	1	0	12	0	130191	119408	47	40100	10100	20000	10002	100	20000	10000	500	6217014	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	3	0	0	1310	1	2	16	2	3	129519	10000	10000	10000	10100	130033	130033	130132	130033	130036
30204	130574	974	0	0	7	0	0	0	130017	119453	25	40100	10100	20000	10000	100	20000	10000	500	6214785	14802709	0	130015	0	130035	130033	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130035	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1335	1	2	16	3	2	129583	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	144	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126243	30100	200	10000	20000	200	10000	20000	130034	130032	1	1	20201	100	99	100	10100	10000	100	0	4	10000	2	2	0	0	0	1310	1	2	16	2	2	129520	10000	10000	10000	10100	130033	130033	130034	130033	130033
30204	130034	974	0	0	0	0	27	0	130018	119408	108	40100	10100	20003	10002	100	20000	10000	500	6214497	14803051	0	130014	0	130032	130116	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130033	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	0	0	0	1310	1	2	16	2	3	129599	10030	10000	10000	10100	130033	130122	130033	130130	130033
30204	130032	985	1	1	26	2	12	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130015	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130033	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	3	0	0	1310	1	2	16	2	2	129521	10000	10000	10000	10100	130033	130033	130034	130033	130033
30204	130032	974	0	0	0	0	0	0	130018	119409	25	40100	10100	20000	10000	100	20000	10000	500	6214641	14802931	1	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	3	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130034	130034	130033
30204	130032	974	0	0	0	0	21	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130035	130034	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	0	0	0	1310	1	3	17	2	2	129519	10000	10000	10000	10100	130037	130034	130033	130034	130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130034	975	0	0	0	0	12	0	130017	119408	47	40010	10010	20003	10000	10	20000	10000	50	6214497	14800756	1	130013	0	130032	130032	125491	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	3	1270	1	17	1	1	129519	10001	10000	10000	10010	130125	130300	130033	130124	130036
30024	130033	975	0	1	0	0	12	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214545	14800528	1	130013	0	130032	130033	125489	3	126262	30010	20	10000	20000	20	10000	20000	130033	130035	1	1	20021	10	9	10	10010	10000	10	10000	0	3	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	12	0	130017	119408	25	40010	10010	20003	10000	10	20113	10049	50	6214497	14800528	1	130013	0	130112	130033	125492	3	126262	30010	20	10000	20000	22	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20238	10000	50	6214497	14800982	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130035
30024	130032	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214881	14800528	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	1270	1	16	1	2	129520	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130133
30024	130032	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	1270	1	16	1	2	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	1270	1	16	1	1	129523	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	1270	2	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	3	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033

Test 3: throughput

Count: 8

Code:

  scvtf h0, x8, #3
  scvtf h1, x8, #3
  scvtf h2, x8, #3
  scvtf h3, x8, #3
  scvtf h4, x8, #3
  scvtf h5, x8, #3
  scvtf h6, x8, #3
  scvtf h7, x8, #3

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	a5	ld unit uop (a6)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26711	199	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26695	26709	26709	6632	0	6	6658	160136	200	80020	80020	200	80020	80020	26709	26792	1	1	80201	100	99	100	100	80000	100	0	80000	0	1	1	1	5117	2	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80024	26753	26874	1	1	80201	100	99	100	100	80000	100	0	80000	0	1	1	1	5117	0	16	0	0	26709	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	1	1	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	199	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	1	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	1	1	1	5117	0	16	0	0	26819	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	1	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26712	200	0	0	0	0	12	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168273	1884032	26694	26713	26713	6657	0	3	6689	160010	20	80000	80000	20	80000	80000	26713	26721	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	5020	0	0	7	16	5	5	26710	80000	80000	10	26710	26714	26710	26715	26710
160024	26709	200	0	0	0	0	12	0	26698	2	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	26694	26713	26709	6653	0	3	6689	160010	20	80381	80000	20	80000	80000	26713	26713	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	1	0	3	0	5020	0	1	6	16	6	5	26706	80000	80000	10	26714	26710	26715	26714	26714
160024	26709	200	0	0	0	0	12	0	26702	5	25	160010	10	80000	80000	10	80000	80000	50	1168880	1874466	26690	26713	26713	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26714	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	1	0	3	0	5020	0	1	7	16	5	6	26706	80000	80000	10	27395	26715	26714	26714	26884
160024	26713	200	0	0	0	0	174	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1167890	1880260	26690	26709	26712	6656	0	3	6693	160010	20	80000	80000	20	80000	80000	26709	26713	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	1	0	3	0	5020	0	0	6	16	5	6	26706	80000	80000	10	26714	26714	26714	26714	26714
160024	26713	200	0	0	0	0	0	0	26698	2	25	160010	10	80000	80000	10	80000	80000	50	1181647	1882853	26690	27215	26716	6654	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26713	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	1	0	3	0	5020	0	0	7	16	6	5	26710	80000	80000	10	26710	26714	26714	26715	26714
160024	26709	200	0	0	0	0	0	0	26698	0	25	160010	10	80000	80000	10	80000	80000	50	1168440	1884012	26690	26709	26713	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26714	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	5020	0	0	5	16	7	7	26710	80000	80000	10	26714	26710	26715	26710	26714
160024	26709	200	0	0	0	0	0	0	26698	2	25	160010	10	80000	80000	10	80000	80000	50	1168707	1883525	26695	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26714	26713	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	1	0	3	0	5020	0	0	7	16	7	5	26709	80000	80000	10	26714	26710	26714	26710	26714
160024	26713	200	0	0	0	0	12	0	26698	2	25	160010	10	80000	80000	10	80000	80000	50	1174994	1882854	26694	26709	26709	6657	0	3	6693	160010	20	80000	80000	20	80000	80000	26713	26714	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	1	0	12	0	5020	0	0	5	16	6	5	26711	80000	80000	10	26714	26714	26714	26710	26715
160024	26713	200	0	0	0	0	12	0	26698	2	25	160010	10	80000	80000	10	80000	80000	50	1170493	1880794	26694	26713	26709	6657	0	3	6689	160010	20	80000	80000	20	80000	80000	26713	26713	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	1	0	3	0	5020	0	0	6	16	6	5	26706	80000	80000	10	26715	26714	26715	26714	26714
160024	26714	200	0	0	0	0	12	0	26698	2	25	160010	10	80000	80000	10	80000	80000	50	1157089	1884052	26694	26710	26713	6653	0	3	6693	160010	20	80000	80000	20	80000	80000	26709	26713	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	5020	0	0	6	16	4	6	26710	80000	80000	10	26710	26714	26714	26714	26714

SCVTF (scalar, fixed-point, H from X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations