Firestorm: SCVTF (scalar, fixed-point, S from W) measurements

Code:

  scvtf s0, w0, #3

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	377	3	0	361	0	25	2000	1000	1130	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	3	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	378	377	377	377
2004	376	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	378	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	2	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	73	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	3	0	73	1	16	1	2	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	2	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	4	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	379	1	1	1001	1000	1000	0	0	73	1	16	1	2	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	2	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	2	373	1000	1000	377	377	377	377	377

Test 2: Latency 1->2 roundtrip

Code:

  scvtf s0, w0, #3
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	974	0	0	1	1	306	0	130021	119409	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	1	3	1310	1	2	16	2	2	129521	10000	10000	10000	10100	130038	130035	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119554	112	40100	10100	20000	10000	100	20000	10000	500	6214785	14802709	130013	130032	130033	125466	3	126241	30100	200	10000	20000	200	10000	20000	130032	130054	1	1	20201	100	99	100	10100	10000	100	0	10000	1	3	1310	1	3	16	3	2	129521	10000	10000	10000	10100	130033	130036	130033	130033	130033
30204	130032	974	0	0	0	0	30	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802825	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	1	3	1310	1	3	16	3	3	129519	10000	10000	10000	10100	130033	130033	130033	130037	130033
30204	130032	974	0	0	0	0	12	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	130013	130032	130032	125495	3	126242	30100	200	10000	20000	200	10000	20000	130032	130083	1	1	20201	100	99	100	10100	10000	100	0	10000	1	3	1310	1	3	16	3	3	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	12	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802941	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	1	0	1310	1	2	16	2	2	129520	10000	10000	10000	10100	130033	130033	130033	130034	130033
30204	130032	974	0	0	0	0	12	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	130013	130034	130035	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	1	3	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130034	130033	130035	130033
30204	130032	973	0	0	0	0	0	0	130017	119410	25	40100	10100	20000	10000	100	20000	10000	500	6214545	14802709	130013	130032	130032	125466	3	126243	30100	200	10000	20000	200	10000	20000	130036	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	1	3	1310	1	3	16	2	2	129520	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	12	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	130013	130032	130032	125467	3	126240	30100	200	10000	20000	200	10000	20000	130032	130052	1	1	20201	100	99	100	10100	10000	100	0	10000	1	3	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130035	130033	130033	130033	130062
30204	130032	973	0	0	0	0	12	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214545	14803048	130013	130032	130032	125468	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	1	3	1310	1	3	16	3	3	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	12	0	130017	119410	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	130013	130032	130033	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	1	0	1336	1	2	16	3	2	129519	10000	10000	10000	10100	130034	130036	130033	130033	130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	2	16	1	1	129520	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	129522	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	46	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	129554	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	3	129539	10000	10000	10000	10010	130033	130033	130033	130036	130033
30024	130032	974	0	0	12	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214545	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	1	3	0	0	0	1270	1	16	1	1	129521	10000	10000	10000	10010	130033	130034	130033	130033	130033
30024	130032	974	0	0	12	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130034	125489	3	126262	30010	20	10000	20000	20	10000	20000	130035	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	1	3	0	0	0	1270	1	16	1	1	129554	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	12	0	130018	119409	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800642	1	130013	130035	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130036	1	1	20021	10	9	10	10010	10000	10	0	0	10000	1	3	0	0	0	1270	1	16	1	1	129545	10000	10000	10000	10010	130033	130033	130036	130033	130033
30024	130035	974	0	0	0	0	130019	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214641	14808070	1	130013	130032	130032	125489	3	126265	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1395	1	79	3	3	129963	10000	10000	10000	10010	130033	130033	130033	130367	130373
30024	130368	974	0	0	909	88	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	1	3	0	0	0	1270	1	16	1	1	129540	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	12	0	130017	119410	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800864	1	130013	130032	130035	125492	3	126262	30010	20	10000	20000	20	10000	20000	130033	130033	1	1	20021	10	9	10	10010	10000	10	0	0	10000	1	3	0	0	0	1270	1	16	1	1	129558	10000	10000	10000	10010	130033	130033	130033	130035	130033

Test 3: throughput

Count: 8

Code:

  scvtf s0, w8, #3
  scvtf s1, w8, #3
  scvtf s2, w8, #3
  scvtf s3, w8, #3
  scvtf s4, w8, #3
  scvtf s5, w8, #3
  scvtf s6, w8, #3
  scvtf s7, w8, #3

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26710	200	26700	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26917	27055	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	26694	6	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	6	6658	160135	200	80020	80024	200	80020	80024	26725	26721	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26718	26710	26710	26710	26710
160204	26709	200	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1885348	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26710	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1174360	1884198	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26715	26710	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26715	200	0	12	26701	3	25	160010	10	80000	80000	10	80000	80000	50	1182125	1884106	1	26690	26714	26709	6657	3	6693	160010	20	80000	80000	20	80000	80000	26713	26713	1	1	80021	10	9	10	10	80000	10	0	0	80000	1	0	3	5020	0	3	16	3	3	26874	80000	80000	10	26714	26714	26710	26714	26714
160024	26713	200	0	12	26699	2	25	160010	10	80000	80000	10	80000	80000	50	1168701	1885392	1	26694	26713	26714	6657	3	6694	160010	20	80000	80000	20	80000	80000	26713	26713	1	1	80021	10	9	10	10	80000	10	0	111	80000	2	0	3	5020	0	2	16	3	3	26712	80000	80000	10	26714	26714	26710	26714	26714
160024	26713	200	0	12	26698	0	25	160010	10	80000	80000	10	80000	80000	50	1170662	1880782	1	26694	26713	26713	6653	3	6693	160010	20	80000	80000	20	80000	80000	26709	26740	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	5020	0	3	16	3	3	26716	80000	80000	10	26714	26714	26714	26714	26714
160024	26710	200	0	12	26698	3	25	160010	10	80000	80000	10	80000	80000	50	1175415	1883847	1	26690	26713	26713	6654	3	6693	160010	20	80000	80000	20	80000	80000	26863	26740	1	1	80021	10	9	10	10	80000	10	0	0	80000	1	0	3	5020	0	3	16	6	3	26717	80000	80000	10	26715	26710	26714	26714	26714
160024	26713	200	0	0	26698	2	25	160010	10	80130	80130	10	80000	80000	50	1168388	1883204	1	26690	26713	26713	6657	3	6693	160010	20	80000	80000	20	80000	80000	26711	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	1	4	881	5020	1	8	16	2	3	26710	80000	80000	10	26714	26710	26714	26714	26710
160024	26713	200	0	12	26698	3	25	160010	10	80000	80000	10	80000	80000	50	1168764	1890194	1	26695	26713	26709	6656	3	6693	160010	20	80000	80000	20	80000	80000	26713	26714	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	3	5020	0	4	16	6	6	26718	80000	80000	10	26715	26714	26710	26714	26714
160024	26709	205	0	12	26698	2	25	160010	10	80000	80000	10	80000	80000	50	1169455	1885322	1	26695	26714	26714	6653	3	6693	160010	20	80000	80000	20	80000	80000	26713	26713	1	1	80021	10	9	10	10	80000	10	0	0	80000	1	0	3	5020	0	3	16	3	2	26736	80000	80000	10	26714	26714	26715	26714	26715
160024	26709	200	0	12	26694	2	25	160010	10	80000	80000	10	80000	80000	50	1168600	1883511	1	26695	26710	26713	6657	3	6694	160010	20	80000	80000	20	80000	80000	26713	26714	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	3	5020	0	6	16	3	2	26718	80000	80000	10	26714	26714	26714	26714	26714
160024	26709	200	0	12	26698	3	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26713	26714	6657	3	6690	160010	20	80000	80000	20	80000	80000	26714	26713	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	3	5020	0	3	16	5	3	26718	80000	80000	10	26715	26714	26715	26710	26714
160024	26709	200	0	0	26698	2	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26714	26713	6653	3	6693	160010	20	80000	80000	20	80000	80000	26713	26713	1	1	80021	10	9	10	10	80000	10	4	0	80000	0	0	3	5020	0	3	16	3	6	26714	80000	80000	10	26710	26710	26714	26714	26710

SCVTF (scalar, fixed-point, S from W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations