Firestorm: SCVTF (scalar, fixed-point, S from X) measurements

Code:

  scvtf s0, x0, #3

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	379	3	0	0	361	25	2000	1000	1000	1000	1000	14075	22872	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	0	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	0	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	0	0	369	25	2000	1000	1000	1000	1000	14075	22985	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	379	377
2004	376	3	0	0	364	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	75	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	378
2004	376	4	0	0	361	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	379	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	0	0	372	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	110	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	1	0	362	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	112	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	0	361	25	2000	1000	1000	1000	1000	14104	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	0	361	25	2000	1000	1000	1000	1000	14225	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377

Test 2: Latency 1->2 roundtrip

Code:

  scvtf s0, x0, #3
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	974	1	1	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130032	130032	125473	7	126235	30100	200	10003	20005	200	10003	20005	130032	130032	1	1	20201	100	99	100	10100	10000	100	10002	0	0	1	1	1	1317	0	2	16	3	2	129527	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	1	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125473	6	126236	30100	200	10003	20005	200	10003	20005	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	6	0	1	1	1	1355	0	2	16	2	2	129532	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	1	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125473	7	126235	30100	200	10003	20005	200	10003	20005	130032	130033	1	1	20201	100	99	100	10100	10000	100	10000	0	0	1	1	1	1318	0	2	16	2	2	129532	10000	10000	10000	10100	130033	130034	130033	130033	130033
30204	130032	974	1	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130032	130032	125473	6	126235	30100	200	10003	20005	200	10003	20005	130032	130043	1	1	20201	100	99	100	10100	10000	100	10000	0	0	1	1	1	1317	0	2	16	2	2	129532	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	1	1	0	1	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125473	7	126236	30100	200	10003	20005	200	10003	20005	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	1	1	1	1318	0	2	16	2	2	129532	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130032	130032	125473	7	126235	30100	200	10003	20005	200	10003	20005	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	1	1	1	1317	0	2	16	2	2	129532	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	1	0	0	1	130018	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125473	6	126235	30100	200	10003	20005	200	10003	20005	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	1	1	1	1317	0	2	16	2	2	129527	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	1	0	0	1	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130032	130032	125473	6	126235	30100	200	10003	20005	200	10003	20005	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	1	1	1	1317	0	2	16	2	2	129527	10000	10000	10000	10100	130064	130033	130033	130033	130033
30204	130032	973	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130032	130032	125473	7	126236	30100	200	10003	20005	200	10003	20005	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	1	1	1	1317	0	2	16	2	2	129527	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130032	130032	125473	6	126235	30100	200	10003	20005	200	10003	20005	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	1	1	1	1317	0	2	16	2	2	129532	10000	10000	10000	10100	130033	130033	130033	130033	130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130032	974	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	3	1270	2	17	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126264	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	1270	2	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	6	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	1270	1	16	1	1	129739	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	12	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30179	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	1270	1	16	1	1	129519	10001	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033

Test 3: throughput

Count: 8

Code:

  scvtf s0, x8, #3
  scvtf s1, x8, #3
  scvtf s2, x8, #3
  scvtf s3, x8, #3
  scvtf s4, x8, #3
  scvtf s5, x8, #3
  scvtf s6, x8, #3
  scvtf s7, x8, #3

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26710	200	0	0	0	0	0	0	0	2	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168396	1884163	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	33	0	3	0	1	1	1	5119	3	16	4	8	26706	0	80000	80000	100	26710	26710	26710	26710	26786
160204	26709	200	0	0	0	0	0	0	0	2	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	0	6	6660	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	0	0	1	1	1	5119	6	16	9	8	26706	0	80000	80000	100	26710	26710	26710	26710	26800
160204	26709	200	0	0	0	0	0	0	0	2	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	33	0	0	0	1	1	1	5119	8	16	9	8	26706	0	80000	80000	100	26710	26710	26710	26710	26839
160204	26709	200	0	0	0	0	0	0	0	2	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	1	0	865	0	1	1	1	5119	8	16	3	8	26706	0	80000	80000	100	26710	26710	26710	26710	26717
160204	26718	200	0	0	0	0	0	213	0	2	26694	29	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	1	0	0	0	1	1	1	5119	8	16	8	9	26706	0	80000	80000	100	26710	26710	26710	26710	26714
160204	26709	200	0	0	0	0	0	0	0	2	26694	2	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884390	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	0	0	1	1	1	5119	8	16	8	9	26706	0	80000	80000	100	26710	26710	26710	26710	26724
160204	26709	200	0	0	0	0	0	0	0	2	26694	8	25	160100	100	80000	80000	100	80020	80015	500	1168951	1891994	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	1	0	0	0	1	1	1	5119	9	16	8	8	26706	0	80000	80000	100	26998	26719	26820	26712	26710
160204	26709	200	0	0	0	0	0	264	88	2	26694	6	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	0	0	2	2	2	5129	9	33	10	10	26707	0	80000	80000	100	26711	26711	26711	26711	26720
160204	27216	200	1	0	0	0	3	0	0	2	26863	0	92	160100	100	80000	80000	100	80023	80018	500	1168352	1883460	1	26691	26710	26715	6621	0	9	6714	160141	200	80781	80215	202	80023	80023	26710	26710	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	69	0	2	2	2	5196	11	52	9	9	26851	0	80000	80000	100	26711	26711	26711	26711	27248
160204	26710	200	0	1	1	0	0	405	88	2	27208	67	25	160100	100	80520	80130	100	80023	80018	500	1168352	1883460	1	26691	27210	27254	6621	0	10	6645	160141	202	80783	80000	200	80000	80573	26710	26710	2	1	80201	100	99	100	100	80000	100	4	0	80000	0	25	0	0	2	1	1	1	5122	10	25	10	10	26707	0	80000	80000	100	27211	26835	26954	27050	26869

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26709	200	0	26694	22	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884206	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	1	0	0	5020	1	16	2	1	26706	80000	80000	10	26710	26710	26710	26710	26717
160024	26709	200	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1170252	1884775	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	1	0	3	5020	1	16	1	1	26706	80000	80000	10	26781	26756	26837	26726	26710
160024	26709	206	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	2	0	1748	5020	1	16	1	1	26706	80000	80000	10	26710	26710	26710	26710	26715
160024	26710	201	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1169605	1884032	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	1	0	0	5020	1	16	1	1	26706	80000	80000	10	26710	26710	26710	26710	26719
160024	26709	200	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	2	1	80021	10	9	10	10	80000	10	80000	1	0	0	5020	1	16	1	1	26706	80000	80000	10	26710	26710	26710	26710	26716
160024	26709	200	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	1	0	3	5020	1	16	1	1	26706	80000	80000	10	26710	26710	26710	26710	26719
160024	26711	200	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	1	0	3	5020	1	16	1	1	26706	80000	80000	10	26710	26710	26710	26710	26719
160024	26715	200	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168435	1884032	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	1	0	3	5020	1	16	1	1	26706	80000	80000	10	26710	26710	26710	26710	26716
160024	26709	199	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	1	0	0	5020	1	16	1	1	26706	80000	80000	10	26710	26710	26710	26710	26719
160024	26709	200	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	1	0	0	5020	1	16	1	1	26706	80000	80000	10	26710	26900	26774	26728	26710

SCVTF (scalar, fixed-point, S from X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations