Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SCVTF (scalar, integer, D from D)

Test 1: uops

Code:

  scvtf d0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037236125472510001000100039816013018303730372414328951000100010003037303711100110000000073316222629100030383038303830383038
10043037236125472510001000100039816013018303730372414328951000100010003037303711100110000000373216222629100030383038303830863038
10043037236125472510001000100039816013018303730372414328951000100010003037303711100110000000073216222629100030383038303830383038
10043037236125472510001000100039816013018303730372414328951000100010003037303711100110000000073216222629100030383038303830383038
10043037236125472510001000100039816013018303730372414328951000100010003037303711100110000000073216222629100030383038303830383038
10043037236125472510001000100039816013018303730372414328951000100010003037303711100110000000073216222629100030383038303830383038
10043037236125472510001000100039816013018303730372414328951000100010003037303711100110000000073216222629100030383038303830383038
10043037236125472510001000100039816013018303730372414328951000100010003037303711100110000000073216222629100030383038303830383038
10043037226125472510001000100039816013018303730372414328951000100010003037303711100110000000073216222629100030383038303830383038
10043037236125472510001000100039816013018303730372414328951000100010003037303711100110000000073216222629100030383038303830383038

Test 2: Latency 1->2

Code:

  scvtf d0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250612954725101001001000010010000500427716030018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
1020430037225910132954725101001001000010010000500427716030018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716030018300373003728264328745101002001000020010000300373003711102011009910010010000100055907101161129633100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716030018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716030018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716030018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
102043003722507262954725101001001000010010000500427716030018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
102043003722502512954725101001001000010010000500427716030018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
102043003722502512954725101001001000010010000500427716030018300373003728264328745101002001000020010000300373008511102011009910010010000100007101161129633100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716030018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000001032954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010001306403162229629010000103003830038300383003830038
1002430037225000000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010001306402162229629010000103003830038300383003830038
100243003722500001201032954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010001306402162229629010000103003830038300383003830038
100243003722500001201032954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010001306402163229629010000103003830038300383003830038
100243003722500001201032954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010001306402162229629010000103003830038300383003830038
100243003722500001201032954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010001306402163329629010000103003830038300383003830038
10024300372250000001032954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010001306402162229629010000103003830038300383003830038
100243003722500001207262954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010001306402162229629010000103003830038300383003830038
1002430037225000012046922948413410071131004815110506642852721302703032030357283162728897110322011139201032530371303208110021109101010000102011953327892642329860510000103031930369303693037330368
100243035622710779485284626294931351006314100561511050504277160030018300373003728286328767100102010000201000030037300371110021109101010000100021763328083812329880510000103041830367303703036630368

Test 3: throughput

Count: 8

Code:

  scvtf d0, d8
  scvtf d1, d8
  scvtf d2, d8
  scvtf d3, d8
  scvtf d4, d8
  scvtf d5, d8
  scvtf d6, d8
  scvtf d7, d8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420061150103025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402011220040
8020420039150003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005015000008225800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000005020015161172003680000102004020040200402004020040
8002420039150001208225800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001001305020011169132003680000102004020040200402004020040
800242003915000008225800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001001305020010161072003680000102004020040200402004020040
80024200391500012082258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010013050201511161192003680000102004020040200402004020040
800242003915000120822580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100130502018916992003680000102004020040200402004020040
80024200391500012082258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010013050201571612112003680000102004020040200402004020040
8002420039150001208225800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001001005020156169112003680000102004020040200402004020040
800242003915000120822580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100000502015111611102003680000102004020040200402004020040
800242003915000120402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100130502015101610102003680000102004020040200402004020040
800242003915000120822580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100130502015111610112003680000102004020040200402004020040