Firestorm: SCVTF (scalar, integer, D from W) measurements

Code:

  scvtf d0, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	379	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	364	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	3	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	1	0	73	1	16	1	1	373	1000	1000	377	377	377	377	378
2004	376	2	0	361	2	25	2000	1000	1000	1000	1000	14075	22820	1	357	379	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	380
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	389	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	3	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	380	377	377	377	377
2004	376	2	0	364	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	376	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377

Test 2: Latency 1->2 roundtrip

Code:

  scvtf d0, w0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	974	0	39	0	130017	119412	25	40100	10100	20000	10000	100	20000	10000	500	6214545	14803054	1	130013	130467	130117	125582	3	126240	30100	200	10000	20000	200	10064	20000	130036	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	4	16	2	2	129520	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130034	974	0	12	0	130017	119408	25	40100	10102	20000	10004	117	20000	10098	500	6222293	14802709	1	130082	130033	130033	125466	3	126301	30429	204	10000	20735	202	10061	20489	130032	130033	3	1	20201	100	99	100	10100	10000	100	10000	0	0	3	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130034
30204	130032	974	0	0	0	130017	119410	25	40100	10100	20003	10000	100	20000	10000	500	6214497	14802824	1	130014	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	2	16	2	2	129521	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	9	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130016	130032	130447	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	973	0	12	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130014	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	973	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1336	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	973	0	9	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130016	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	2	16	2	2	129522	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130036	130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130032	974	0	0	0	0	12	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130014	130035	130033	125489	3	126262	30010	20	10000	20000	20	10000	20000	130033	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	1	0	3	0	1270	5	16	2	2	129519	10000	10000	10000	10010	130035	130035	130033	130033	130033
30024	130032	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130016	130032	130037	125489	3	126263	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	1	0	0	0	1270	2	16	2	3	129519	10000	10000	10000	10010	130033	130033	130035	130033	130033
30024	130033	974	0	0	0	0	12	0	130019	119409	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130039	130032	125490	3	126263	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	1	0	3	0	1270	2	16	2	2	129519	10000	10000	10000	10010	130033	130033	130033	130036	130033
30024	130036	973	0	0	0	0	12	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125490	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	1	0	3	0	1270	2	16	2	1	129573	10000	10000	10000	10010	130033	130033	130033	130035	130033
30024	130032	974	0	0	0	0	12	0	130017	119409	25	40010	10010	20000	10000	10	20000	10000	50	6214545	14800528	1	130013	130032	130035	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	1	0	3	2	1270	3	16	5	3	129519	10000	10000	10000	10010	130033	130033	130033	130033	130034
30024	130032	974	0	0	0	0	12	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214545	14800528	1	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130033	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	1	0	3	0	1270	2	16	4	3	129522	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130035	974	0	0	0	0	12	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214641	14800528	0	130013	130034	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	1	0	0	0	1270	4	16	2	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126264	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10001	0	1	0	3	0	1270	2	16	2	3	129519	10000	10000	10000	10010	130033	130033	130035	130033	130033
30024	130032	974	0	0	0	0	12	0	130017	119409	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800758	0	130015	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	6	0	1270	2	16	4	3	129520	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126263	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	2	1270	4	16	4	4	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033

Test 3: throughput

Count: 8

Code:

  scvtf d0, w8
  scvtf d1, w8
  scvtf d2, w8
  scvtf d3, w8
  scvtf d4, w8
  scvtf d5, w8
  scvtf d6, w8
  scvtf d7, w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26709	200	12	0	26698	1	25	160100	100	80000	80000	100	80020	80015	500	1169746	1880936	0	26709	26709	26710	6636	6	6662	160135	200	80024	80020	200	80024	80024	26713	26713	1	1	80201	100	99	100	100	80000	100	80000	1	0	0	1	1	1	5117	2	16	0	1	2	26710	80000	80000	100	26715	26714	26714	26714	26714
160204	26709	200	12	0	26698	2	25	160100	100	80000	80000	100	80020	80016	500	1168951	1884163	0	26694	26713	26713	6636	6	6662	160134	200	80020	80020	200	80020	80020	26714	26713	1	1	80201	100	99	100	100	80000	100	80000	1	3	0	1	1	1	5117	1	16	0	1	2	26711	80000	80000	100	26714	26710	26714	26714	26714
160204	26713	200	12	0	26698	2	25	160100	100	80000	80000	100	80020	80015	500	1169734	1883950	0	26700	26713	26713	6636	6	6662	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	1	3	0	1	1	1	5117	3	16	0	2	3	26710	80000	80000	100	26710	26710	26714	26714	26714
160204	26709	200	12	0	26698	2	25	160100	100	80000	80000	100	80020	80016	500	1168951	1882335	0	26694	26713	26713	6636	6	6662	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	1	3	0	1	1	1	5117	2	16	0	2	1	26706	80000	80000	100	26714	26715	26710	26710	26714
160204	26713	200	12	0	26698	2	25	160100	100	80000	80000	100	80020	80015	500	1170238	1882780	0	26700	26713	26713	6636	6	6658	160135	200	80020	80020	200	80024	80024	26713	26713	1	1	80201	100	99	100	100	80000	100	80000	1	0	0	1	1	1	5117	2	16	0	2	1	26710	80000	80000	100	26714	26714	26714	26710	26714
160204	26714	200	0	0	26694	3	25	160100	100	80000	80000	100	80020	80014	500	1169667	1883853	0	26690	26713	26713	6636	6	6662	160135	200	80020	80024	200	80020	80020	26714	26713	1	1	80201	100	99	100	100	80000	100	80000	1	0	0	1	1	1	5117	2	16	0	2	2	26710	80000	80000	100	26715	26714	26714	26710	26715
160204	26709	200	12	0	26694	0	25	160100	100	80000	80000	100	80024	80014	500	1168931	1884165	0	26694	26713	26713	6632	25	6662	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	1	3	0	1	1	1	5117	2	16	0	2	1	26710	80000	80000	100	26715	26714	26714	26714	26715
160204	26713	200	12	0	26697	2	25	160100	100	80000	80000	100	80020	80015	500	1168278	1884205	0	26694	26710	26714	6636	6	6662	160135	200	80020	80020	200	80020	80024	26713	26713	1	1	80201	100	99	100	100	80000	100	80000	1	3	0	1	1	1	5117	2	16	0	2	2	26710	80000	80000	100	26714	26710	26710	26714	26715
160204	26713	200	12	0	26698	3	25	160100	100	80000	80000	100	80020	80015	500	1160713	1888450	0	26694	26709	26709	6636	6	6659	160134	200	80020	80020	200	80020	80020	26709	26713	1	1	80201	100	99	100	100	80000	100	80000	0	0	0	1	1	1	5117	2	16	0	2	2	26711	80000	80000	100	26714	26714	26714	26714	26714
160204	26713	200	12	0	26694	2	25	160100	100	80000	80000	100	80020	80014	500	1168126	1881613	0	26699	26714	26713	6632	6	6661	160133	200	80020	80020	200	80024	80020	26713	26709	1	1	80201	100	99	100	100	80000	100	80000	1	3	0	1	1	1	5117	2	16	0	2	2	26710	80000	80000	100	26710	26714	26714	26715	26710

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26710	200	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26736	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	5020	16	16	13	14	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	15	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26695	26709	26720	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26815	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	4	0	0	5020	15	16	14	14	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	199	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26698	26709	26709	6665	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	5020	13	16	13	11	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26691	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	5020	13	16	13	14	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26700	26709	26709	6653	0	3	6692	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	5020	12	16	14	9	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26701	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	5020	8	16	14	12	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26701	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	5020	16	16	13	13	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26699	26716	26713	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	5020	12	16	11	11	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26699	26712	26715	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	5020	12	16	14	14	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26701	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26711	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	5020	13	16	8	12	26706	80000	80000	10	26710	26714	26710	26710	26710

SCVTF (scalar, integer, D from W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations