Firestorm: SCVTF (scalar, integer, H from W) measurements

Code:

  scvtf h0, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	3	0	0	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	0	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	0	1000	1	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	0	0	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	0	3	109	2000	1000	1000	1000	1000	389	376	1	1	1001	1000	0	1000	0	3	0	73	1	16	1	1	373	1000	1000	377	377	377	381	377
2004	376	2	0	0	0	372	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	0	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	0	1000	0	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	0	0	0	361	2	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	0	3	109	2000	1000	1000	1000	1189	378	376	1	1	1001	1000	0	1000	0	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	380
2004	376	2	0	0	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	0	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	0	1000	0	0	0	73	1	16	1	1	373	1000	1000	377	377	377	380	377
2004	376	3	0	0	0	371	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	0	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	0	1000	0	0	0	73	1	16	1	1	373	1000	1000	377	377	378	377	377
2004	376	3	0	0	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	0	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	0	1000	0	0	0	73	1	16	1	1	373	1000	1000	377	381	377	377	377
2004	376	3	0	0	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	0	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	0	1000	0	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	0	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	0	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	0	1000	0	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	0	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	0	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	0	1000	0	0	0	73	1	16	1	1	377	1000	1000	377	377	377	377	377

Test 2: Latency 1->2 roundtrip

Code:

  scvtf h0, w0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	974	0	3	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214545	14802709	0	130013	130032	130032	125466	3	126240	30100	202	10000	20000	200	10000	20000	130034	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	41	0	3	0	1310	1	2	16	2	2	129519	10027	10000	10000	10100	130034	130033	130034	130033	130044
30204	130032	974	0	0	0	130017	119408	25	40100	10115	20000	10002	100	20000	10000	500	6214497	14803669	0	130107	130032	130032	125466	3	126240	30100	200	10000	20000	202	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	3	0	3	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130034
30204	130032	974	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130016	130032	130119	125466	3	126240	30100	200	10061	20000	200	10000	20000	130119	130033	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	2	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	133420	133651	133056	133585	134021
30204	133476	1029	7	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	49	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130059
30204	130032	974	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	59	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130065
30204	130032	974	0	9	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	2	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130062
30204	130032	974	0	0	0	130017	119408	25	40100	10100	20006	10002	100	20000	10000	500	6214497	14802709	0	130013	130124	130032	125466	3	126241	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	65	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130051
30204	130032	974	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	55	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	973	0	12	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10067	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	41	0	3	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130084
30204	130032	974	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	130032	130032	125467	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130041

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130032	974	0	0	0	30	130017	119441	68	40010	10016	20000	10000	10	20000	10049	50	6221917	14800528	0	130013	0	130032	130034	125491	3	126295	30820	20	10000	20000	20	10000	20000	130121	130205	1	1	20021	10	9	10	10010	10000	10	10000	0	3	1270	1	16	5	1	129520	10000	10000	10000	10010	130033	130034	130036	130033	130033
30024	130032	974	0	0	0	12	130017	119410	25	40010	10010	20000	10000	10	20000	10000	50	6214641	14800528	1	130013	0	130032	130032	125489	3	126314	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10004	3	3	1272	5	16	1	1	129519	10000	10000	10000	10010	130033	130033	130034	130033	130036
30024	130033	999	0	0	0	12	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800861	1	130013	0	130032	130032	125493	3	126298	30010	20	10000	20000	20	10000	20000	130062	130032	1	1	20021	10	9	10	10010	10000	10	10000	9	3	1270	2	16	1	1	129519	10000	10000	10000	10010	130033	130034	130036	130036	130033
30024	130033	975	0	1	0	48	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800870	1	130013	3	130032	130034	125489	3	126303	30010	20	10000	20000	20	10000	20000	130032	130033	1	1	20021	10	9	10	10010	10000	10	10000	1	0	1270	1	16	2	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800640	1	130013	0	130039	130036	125489	3	126311	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	1	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130036	130033	130033	130035	130035
30024	130034	995	0	0	0	12	130017	119410	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800979	1	130013	0	130036	130032	125489	3	126315	30010	20	10000	20000	20	10000	20000	130032	130035	1	1	20021	10	9	10	10010	10000	10	10000	1	3	1272	1	16	1	2	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126308	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130114	130033	130033	130033	130033
30024	130032	974	0	0	1	1029	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126313	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	1270	1	16	2	1	129519	10000	10000	10000	10010	130033	130063	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126300	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	1270	1	16	2	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126306	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	1	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033

Test 3: throughput

Count: 8

Code:

  scvtf h0, w8
  scvtf h1, w8
  scvtf h2, w8
  scvtf h3, w8
  scvtf h4, w8
  scvtf h5, w8
  scvtf h6, w8
  scvtf h7, w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26713	199	0	12	26698	2	25	160100	100	80000	80000	100	80020	80014	500	1173942	1884424	1	26694	26714	26713	6636	6	6662	160134	200	80024	80024	200	80020	80024	26709	26713	1	1	80201	100	99	100	100	80000	100	0	0	80000	36	0	0	0	1	1	1	5117	0	16	0	26706	0	80000	80000	100	26714	26714	26714	26714	26854
160204	26713	200	0	12	26699	0	25	160100	100	80000	80000	100	80020	80016	500	1168166	1883898	1	26690	26713	26713	6636	6	6662	160136	200	80020	80020	200	80020	80020	26713	26713	1	1	80201	100	99	100	100	80000	100	0	0	80000	36	0	3	0	1	1	1	5117	0	16	0	26711	0	80000	80000	100	26710	26710	26919	26800	26723
160204	26713	200	0	12	26698	2	25	160100	100	80000	80000	100	80020	80015	500	1178787	1884163	0	26694	26714	26713	6636	6	6662	160134	200	80020	80024	200	80020	80024	26713	26713	1	1	80201	100	99	100	100	80000	100	0	0	80000	4	0	3	0	1	1	1	5117	0	16	0	26710	0	80000	80000	100	26715	26714	26710	26710	26742
160204	26753	201	0	12	26698	2	25	160100	100	80000	80000	100	80208	80199	500	1168951	1888873	1	26694	26709	26713	6636	6	6662	160134	200	80020	80020	200	80020	80020	26709	26714	1	1	80201	100	99	100	100	80000	100	0	0	80000	25	0	935	0	1	1	1	5117	0	16	0	26710	0	80000	80000	100	26714	26710	26710	26714	26962
160204	26713	200	0	0	26694	1	25	160100	100	80000	80000	100	80020	80015	500	1168951	1886254	1	26694	26713	26709	6636	6	6662	160135	200	80020	80020	200	80020	80020	26714	26713	1	1	80201	100	99	100	100	80000	100	0	0	80000	35	0	0	0	1	1	1	5117	0	16	0	26710	0	80000	80000	100	26714	26715	26895	26741	26723
160204	26713	200	0	0	26698	2	25	160100	100	80000	80000	100	80020	80014	500	1168605	1884775	1	26694	26713	26710	6632	6	6662	160134	200	80020	80020	200	80024	80020	26713	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	68	0	6	0	1	1	1	5117	0	16	0	26706	0	80000	80000	100	26710	26714	26710	26715	26950
160204	26715	200	0	12	26694	7	25	160100	100	80000	80000	100	80020	80015	500	1168951	1889012	0	26694	26713	26709	6632	6	6662	160135	200	80020	80020	200	80020	80020	26709	26713	1	1	80201	100	99	100	100	80000	100	0	0	80000	61	0	6	0	1	1	1	5117	0	16	0	26711	0	80000	80000	100	26710	26714	26710	26710	26919
160204	26715	200	0	12	26694	2	25	160100	100	80000	80000	100	80020	80016	500	1170059	1884163	1	26694	26713	26713	6636	6	6658	160135	200	80020	80020	200	80024	80020	26713	26713	1	1	80201	100	99	100	100	80000	100	0	0	80000	42	0	3	0	1	1	1	5117	0	16	0	26710	0	80000	80000	100	26714	26714	26714	26714	26712
160204	26712	200	0	0	26694	2	25	160100	100	80000	80000	100	80396	80015	500	1178852	1885157	0	26694	26713	26714	6632	6	6659	160136	200	80020	80020	200	80024	80020	26714	26710	1	1	80201	100	99	100	100	80000	100	0	0	80000	68	0	9	0	1	1	1	5117	0	16	0	26710	0	80000	80000	100	26714	26715	26710	26710	26949
160204	26713	200	0	12	26699	3	25	160100	100	80000	80000	100	80020	80014	500	1168597	1884201	1	26691	26709	26714	6636	6	6662	160135	200	80024	80020	200	80020	80024	26713	26713	1	1	80201	100	99	100	100	80000	100	0	0	80000	5	0	0	0	1	1	1	5117	0	16	0	26710	0	80000	80000	100	26715	26710	26714	26710	26895

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26710	200	0	0	26694	1	25	160010	10	80000	80000	10	80000	80000	50	1168880	1883443	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	63	0	0	5020	8	16	5	3	26706	80000	80000	10	26710	26710	26710	26710	26929
160024	26715	200	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168568	1884032	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	59	0	6	5020	5	16	6	4	26706	80000	80000	10	26710	26710	26710	26710	26935
160024	26722	200	0	0	26694	4	25	160790	10	80000	80000	10	80000	80000	50	1183157	1884032	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	60	0	9	5020	3	16	3	5	26706	80000	80000	10	26710	26710	26710	26710	26934
160024	26724	200	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	61	0	9	5020	6	16	6	4	26706	80000	80000	10	26710	26710	26710	26710	26944
160024	26721	200	0	0	26694	9	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	67	0	15	5020	3	16	6	4	26706	80000	80000	10	26710	26710	26710	26710	26945
160024	26720	200	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6655	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	63	0	9	5020	6	16	5	3	26706	80000	80000	10	26710	26710	26710	26710	26934
160024	26730	200	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	44	0	0	5020	3	16	5	5	26706	80000	80000	10	26710	26710	26710	26710	26948
160024	26720	200	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1176821	1883681	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	69	0	3	5020	3	16	3	5	26706	80000	80000	10	26710	26710	26710	26710	26961
160024	26722	200	0	0	26694	17	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	68	0	3	5020	5	16	5	5	26706	80000	80000	10	26710	26710	26710	26710	26816
160024	26709	200	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	70	0	6	5020	5	16	4	6	26706	80000	80000	10	26710	26710	26710	26710	26954

SCVTF (scalar, integer, H from W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations