Firestorm: SCVTF (scalar, integer, H from X) measurements

Code:

  scvtf h0, x0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	2	24	361	0	25	2000	1000	1000	1000	1000	14075	22870	1	357	376	376	73	3	110	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	9	362	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	112	2000	1000	1000	1000	1000	376	379	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	380
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	381	377
2004	376	2	0	361	2	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	114	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	23016	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	1	0	73	1	16	1	1	373	1000	1000	377	377	377	377	380
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	111	2000	1000	1000	1000	1000	376	377	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	128	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	362	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	114	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22949	1	357	376	376	72	3	115	2000	1000	1000	1000	1000	379	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	374	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14125	22820	1	357	376	376	72	3	115	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377

Test 2: Latency 1->2 roundtrip

Code:

  scvtf h0, x0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	974	0	0	0	0	130017	119447	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	0	100	10100	10000	100	0	10000	0	3	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130037	130033	130080	130046	130033
30204	130032	974	0	0	0	0	130017	119430	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	0	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130036	130100	130071	130033
30204	130032	974	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	0	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	3	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130080	130033
30204	130032	974	0	0	0	0	130017	119433	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	0	100	10100	10000	100	0	10000	0	1	0	9	2	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130079	130033
30204	130032	974	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	0	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	3	16	2	3	129519	10000	10000	10000	10100	130033	130033	130033	130063	130033
30204	130032	974	0	0	0	0	130017	119415	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	0	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130088	130063	130033
30204	130032	974	0	0	0	0	130017	119428	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	0	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130097	130059	130034
30204	130032	974	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214641	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	0	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129542	10000	10000	10000	10100	130033	130070	130057	130034	130033
30204	130032	974	0	0	0	0	130017	119410	150	40107	10100	20000	10000	100	20352	10294	511	6214497	14802709	1	130013	130527	130032	125507	3	126240	30100	200	10000	20000	202	10000	20000	130032	130032	1	1	20201	100	99	0	100	10100	10000	100	2	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130080	130079	130036	130033
30204	130032	974	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	0	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130075	130036	130034	130033	130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130032	974	0	0	12	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6217377	14800641	0	130015	130032	130033	125489	3	126262	30010	20	10000	20000	20	10000	20000	130036	130032	1	1	20021	10	9	10	10010	10000	10	10000	1	0	3	0	0	1270	2	16	1	1	129519	10000	0	10000	10000	10010	130033	130033	130033	130033	130033
30024	130034	974	0	0	12	130017	119409	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14807005	1	130013	130032	130032	125490	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	1	0	3	0	0	1270	1	16	1	1	129519	10000	0	10000	10000	10010	130033	130033	130033	130033	130035
30024	130032	974	0	0	12	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6216897	14803923	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	1	0	0	0	0	1270	1	16	1	1	129519	10000	0	10000	10000	10010	130033	130033	130033	130035	130033
30024	130035	974	0	0	12	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14807340	1	130014	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	1	0	3	0	0	1270	1	16	2	1	129519	10000	0	10000	10000	10010	130033	130033	130033	130034	130033
30024	130032	974	0	0	66	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6217245	14800983	1	130013	130032	130034	125489	3	126262	30010	20	10000	20000	20	10000	20000	130036	130033	1	1	20021	10	9	10	10010	10000	10	10000	1	0	3	0	0	1270	1	16	1	1	129519	10000	0	10000	10000	10010	130033	130033	130033	130033	130033
30024	130065	974	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6215601	14804151	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	1270	1	16	1	1	129519	10000	0	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14804731	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	1270	2	16	1	1	129519	10000	229	10000	10000	10010	130035	130033	130033	130033	130033
30024	130032	974	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6216225	14804991	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	1270	1	16	1	1	129519	10000	0	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6216753	14803023	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	1270	1	16	1	1	129519	10000	0	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	130021	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	30	0	0	1270	2	16	2	1	129520	10000	0	10000	10000	10010	130033	130033	130033	130033	130033

Test 3: throughput

Count: 8

Code:

  scvtf h0, x8
  scvtf h1, x8
  scvtf h2, x8
  scvtf h3, x8
  scvtf h4, x8
  scvtf h5, x8
  scvtf h6, x8
  scvtf h7, x8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26716	200	0	12	26711	3	25	160100	100	80000	80000	100	80020	80014	500	1172036	1884045	0	26694	26709	26713	6636	6	6663	160135	200	80024	80020	200	80024	80020	26709	26713	1	1	80201	100	99	100	100	80000	100	0	80000	0	3	1	1	1	5117	0	16	0	0	26710	80000	80000	100	26813	26743	26722	26715	26710
160204	26714	206	0	12	26694	2	25	160100	100	80000	80000	100	80020	80014	511	1168951	1881571	0	26690	26709	26709	6636	6	6660	160135	200	80024	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	0	26715	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	0	26708	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80024	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	6	6658	160135	200	80024	80024	200	80024	80020	26709	26718	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	6	6658	160135	200	80024	80020	200	80020	80020	26719	26716	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26713	26715	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	6	6840	160134	200	80020	80020	200	80020	80020	26711	26787	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26715	26814	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26711	200	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26718	26717	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	0	5020	19	16	0	8	8	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	26694	8	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	0	5020	5	16	0	8	8	26708	80000	80000	10	26966	26727	26720	26715	26710
160024	26709	200	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26710	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	0	5020	9	16	0	4	7	26706	80000	80000	10	26964	26718	26720	26719	26710
160024	26709	199	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	3	0	0	0	5020	10	16	0	9	6	26706	80000	80000	10	26969	26727	26720	26720	26710
160024	26709	200	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	0	5020	5	16	0	9	13	26706	80000	80000	10	26803	26717	26883	26713	26710
160024	26709	200	0	26694	3	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26713	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	3	0	5020	6	16	0	6	8	26706	80000	80000	10	26957	26719	26798	26718	26712
160024	26709	200	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	0	5020	6	16	0	5	8	26706	80000	80000	10	26804	26716	26809	26712	26710
160024	26709	200	0	26694	5	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	0	5020	10	16	0	5	7	26706	80000	80000	10	26978	26727	26721	26720	26710
160024	26709	200	0	26694	4	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80132	0	0	0	0	0	5020	9	16	0	10	9	26706	80000	80000	10	26992	26854	26720	26721	26710
160024	26709	200	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	0	5020	6	16	0	7	8	26706	80000	80000	10	26817	26718	26861	26710	26710

SCVTF (scalar, integer, H from X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations