Firestorm: SCVTF (scalar, integer, S from W) measurements

Code:

  scvtf s0, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	2	16	2	1	373	1000	1000	377	377	377	377	378
2004	376	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	379	1	1	1001	1000	1000	0	0	73	2	16	2	2	373	1000	1000	377	377	380	377	379
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377
2004	376	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377
2004	376	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	377	376	1	1	1001	1000	1000	0	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377
2004	376	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	377	376	1	1	1001	1000	1000	0	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	2	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22930	1	358	376	376	72	3	109	2000	1000	1000	1000	1000	376	379	1	1	1001	1000	1000	0	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377
2004	376	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377

Test 2: Latency 1->2 roundtrip

Code:

  scvtf s0, w0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	974	0	0	0	0	0	0	130017	119409	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	5	0	0	0	1310	1	6	16	3	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20127	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130037	130033	130033	130033	130033
30204	130032	974	1	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	3	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	1	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802821	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	9	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130014	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119476	25	40100	10100	20000	10000	100	20116	10000	500	6214497	14802709	0	130013	0	130033	130032	125509	15	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10003	3	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130068
30204	130032	974	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130033	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	3	10000	1	2	8568	2	1310	1	6	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119409	25	40100	10100	20000	10000	100	20000	10000	500	6214641	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	3	0	1310	0	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130018	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130032	974	0	12	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214593	14800528	0	0	130013	130032	130032	125489	3	126264	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	6	0	0	0	1270	5	16	5	3	129519	10000	10000	10000	10010	130040	130036	130033	130035	130033
30024	130032	974	0	12	130017	119410	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	130032	130032	125491	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	1	3	0	0	0	1270	5	16	3	5	129519	10000	10000	10000	10010	130077	130036	130033	130033	130033
30024	130032	974	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130016	130033	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	1	3	0	0	0	1272	4	16	4	5	129519	10000	10000	10000	10010	130049	130039	130034	130033	130036
30024	130032	974	0	12	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214593	14800528	0	0	130016	130032	130032	125489	3	126262	30012	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	1	3	0	0	0	1270	6	16	5	4	129519	10000	10000	10000	10010	130034	130036	130034	130033	130033
30024	130032	974	0	12	130017	119408	25	40010	10010	20000	10000	12	20000	10000	60	6214497	14800528	0	0	130013	130032	130033	125491	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	1	3	0	0	0	1270	5	16	3	5	129520	10000	10000	10000	10010	130120	130195	130046	130034	130033
30024	130032	974	0	12	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800752	0	0	130014	130034	130033	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	3	0	0	0	1270	4	16	7	5	129519	10000	10000	10000	10010	130071	130034	130033	130033	130034
30024	130032	974	0	12	130018	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	130033	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	1	0	0	0	0	1270	5	16	5	6	129519	10000	10000	10000	10010	130037	130033	130033	130033	130036
30024	130033	974	0	12	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800876	0	0	130013	130032	130033	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	1	3	0	0	0	1270	4	16	4	6	129519	10000	10000	10000	10010	130033	130033	130034	130036	130033
30024	130032	974	0	12	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	130034	130032	125490	3	126266	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	1	3	0	0	0	1270	4	16	4	5	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	12	130017	119410	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	130032	130035	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	1270	4	16	4	5	129519	10000	10000	10000	10010	130360	130050	130034	130037	130033

Test 3: throughput

Count: 8

Code:

  scvtf s0, w8
  scvtf s1, w8
  scvtf s2, w8
  scvtf s3, w8
  scvtf s4, w8
  scvtf s5, w8
  scvtf s6, w8
  scvtf s7, w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26716	200	0	0	2	0	12	0	26699	0	25	160100	100	80000	80000	100	80020	80015	500	1159568	1884163	26694	26713	26713	6636	6	6662	160135	200	80024	80024	200	80024	80020	26713	26713	1	1	80201	100	99	100	100	80000	100	80000	0	3	1	1	1	5117	0	16	0	0	26710	80000	80000	100	26714	26715	26710	26714	26714
160204	26709	200	0	0	0	0	12	0	26699	2	25	160100	100	80000	80000	100	80020	80015	500	1170532	1884163	26694	26714	26713	6636	6	6662	160135	200	80020	80020	200	80024	80024	26713	26709	1	1	80201	100	99	100	100	80000	100	80000	1	3	1	1	1	5117	0	16	0	0	26710	80000	80000	100	26714	26710	26714	26715	26714
160204	26714	199	0	0	0	0	0	0	26698	2	25	160100	100	80000	80000	100	80020	80015	500	1168482	1879130	26696	26714	26710	6624	9	6651	160141	200	80027	80023	200	80023	80023	26714	26714	1	1	80201	100	99	100	100	80000	100	80000	0	3	2	2	2	5127	1	24	1	1	26711	80000	80000	100	26716	26715	26716	26715	26711
160204	26714	200	0	0	0	0	12	0	26700	3	25	160100	100	80000	80000	100	80023	80017	500	1168398	1882731	26696	26714	26715	6621	10	6649	160141	200	80023	80023	200	80023	80023	26715	26710	1	1	80201	100	99	100	100	80000	100	80000	1	3	2	2	2	5128	1	24	1	1	26711	80000	80000	100	26714	26711	26711	26715	26715
160204	26710	200	0	0	0	0	12	0	26774	3	25	160100	100	80000	80000	100	80023	80018	500	1174129	1883831	26695	26714	26710	6624	9	6647	160141	200	80023	80023	200	80023	80023	26714	26710	1	1	80201	100	99	100	100	80000	100	80000	1	0	2	2	2	5127	1	24	1	1	26711	80000	80000	100	26715	26715	26711	26715	26715
160204	26714	200	0	0	0	0	12	0	26708	2	25	160100	100	80000	80000	100	80023	80018	500	1175029	1884058	26691	26714	26714	6625	10	6646	160141	200	80023	80023	200	80023	80023	26715	26715	1	1	80201	100	99	100	100	80000	100	80000	1	905	2	2	2	5128	2	42	1	1	26865	80000	80000	100	26888	26892	26888	26891	27009
160204	27405	201	1	1	1	1	291	208	27032	122	95	160622	100	80260	80000	100	80208	80017	500	1174761	1883762	26696	26714	26713	6625	9	6649	160141	200	80023	80023	200	80023	80023	26717	26713	1	1	80201	100	99	100	100	80000	100	80000	2	3	2	2	2	5128	1	24	1	1	26711	80000	80000	100	26715	26711	26715	26715	26715
160204	26714	200	0	0	0	0	12	0	26838	2	25	160100	100	80000	80000	100	80023	80017	500	1180282	1883460	26691	26714	26713	6621	9	6650	160141	200	80027	80023	200	80027	80023	26713	26715	1	1	80201	100	99	100	100	80000	100	80000	1	0	2	2	2	5127	1	24	1	1	26712	80000	80000	100	26715	26714	26715	26711	26716
160204	26710	200	0	0	0	0	12	0	26703	3	25	160100	100	80000	80000	100	80023	80018	500	1167427	1881734	26696	26710	26714	6625	9	6646	160141	200	80023	80023	200	80023	80023	26715	26715	1	1	80201	100	99	100	100	80000	100	80000	1	3	2	2	2	5127	1	24	1	1	26711	80000	80000	100	26715	26715	26715	26711	26711
160204	26714	200	0	0	0	0	12	0	26699	2	25	160100	100	80000	80000	100	80023	80018	500	1169571	1883369	26695	26710	26713	6625	9	6650	160142	200	80023	80023	200	80023	80027	26714	26714	1	1	80201	100	99	100	100	80000	100	80000	1	0	2	2	2	5127	1	24	1	1	26711	80000	80000	100	26727	26716	26715	26711	26715

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26709	200	0	0	0	0	0	0	0	26723	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	26693	26710	26714	6656	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	5020	0	2	16	2	2	26706	0	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	0	0	0	26714	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	5020	0	1	16	1	1	26706	0	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	0	0	0	26701	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	5020	0	1	16	2	2	26706	0	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	5020	0	1	16	1	1	26706	0	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	0	0	0	26702	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	26690	26709	26709	6656	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	5020	0	1	16	1	1	26706	0	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	5020	0	1	16	1	1	26706	0	80000	80000	10	26714	26716	26737	26878	26710
160024	26709	200	0	0	0	4	0	0	0	26696	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	5020	0	2	16	1	1	26706	0	80000	80000	10	26710	26710	26711	26712	26710
160024	26713	200	0	0	0	0	0	0	0	26705	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	5020	0	1	16	1	1	26706	0	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	0	0	0	26704	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	5020	0	1	16	1	1	26706	0	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	199	0	0	0	0	0	0	0	26698	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	5020	0	1	16	1	1	26706	0	80000	80000	10	26710	26710	26710	26710	26710

SCVTF (scalar, integer, S from W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations