Firestorm: SCVTF (scalar, integer, S from X) measurements

Code:

  scvtf s0, x0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	1f	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	2	0	0	0	361	2	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	2	16	3	3	373	1000	1000	377	377	377	381	377
2004	376	3	0	0	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	3	16	3	3	373	1000	1000	377	377	377	377	377
2004	376	3	0	0	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	112	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	3	16	3	3	373	1000	1000	377	377	377	377	377
2004	376	2	0	0	0	361	0	25	2000	1000	1000	1000	1000	14207	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	3	16	3	3	373	1000	1000	377	377	377	377	377
2004	376	3	0	0	0	361	21	25	2000	1000	1000	1000	1000	14075	22820	358	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	3	16	3	3	373	1000	1000	377	377	380	377	377
2004	376	3	0	0	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	3	16	3	3	373	1000	1000	377	377	377	377	377
2004	376	3	0	0	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	379	376	72	3	109	2000	1000	1000	1000	1000	392	376	1	1	1001	1000	1000	0	0	73	3	16	3	3	373	1000	1000	377	377	377	377	377
2004	376	3	0	0	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	75	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	3	16	3	3	373	1000	1000	377	377	377	377	377
2004	376	3	0	0	0	363	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	111	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	3	16	3	3	373	1000	1000	379	377	377	377	377
2004	376	3	0	0	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	3	16	3	3	373	1000	1000	377	377	377	377	377

Test 2: Latency 1->2 roundtrip

Code:

  scvtf s0, x0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	974	0	0	4	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130037	130032	125466	3	126240	30100	202	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130034	974	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130039	130034	125466	3	126242	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	2	10000	0	0	0	3	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130037	130033
30204	130033	974	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130034	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	6	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130053	130037	125466	3	126240	30458	200	10060	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130066	130034	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	48	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130033	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	2	0	3	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130064	130035
30204	130032	974	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802941	1	130013	0	130050	130033	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129521	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130047	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	2	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130038	130033	130033	130033
30204	130032	974	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802823	0	130013	0	130060	130033	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	1	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130067	130034	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130034	974	0	0	0	0	120	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14801504	1	130013	130032	130032	125489	3	126268	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1306	1	16	1	3	129519	10000	10000	10000	10010	130033	130033	130033	130033	130036
30024	130032	974	0	0	0	1	909	0	130019	119408	25	40016	10010	20000	10000	11	20000	10000	50	6233868	14807028	0	130013	130033	130032	125489	3	126264	30010	20	10124	20000	20	10000	20000	130458	130034	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	1	1	129521	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	1080	0	130018	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	1	0	2	0	1270	1	75	1	1	129519	10003	10000	10000	10010	130033	130131	130034	130033	130033
30024	130032	1168	0	0	0	0	228	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126263	30010	20	10000	20000	20	10000	20000	130032	130032	2	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	2	1	129519	10000	10000	10000	10010	130033	130033	130068	130033	130033
30024	130032	1008	1	1	0	0	276	352	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126263	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130065	130033	130033	130033
30024	130032	974	0	0	0	0	120	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	840	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130044
30024	130032	986	0	0	0	0	186	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	159	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	63	352	130019	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800873	1	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	1	2	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033

Test 3: throughput

Count: 8

Code:

  scvtf s0, x8
  scvtf s1, x8
  scvtf s2, x8
  scvtf s3, x8
  scvtf s4, x8
  scvtf s5, x8
  scvtf s6, x8
  scvtf s7, x8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26715	200	0	0	0	0	12	0	0	26698	2	25	160100	100	80000	80000	100	80020	80015	500	1165304	1884291	1	26694	26713	26710	6636	6	6662	160135	200	80020	80024	200	80020	80020	26713	26713	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	11	0	12	0	1	1	1	5117	0	16	0	0	26710	0	0	80000	80000	100	26710	26710	26710	26710	26719
160204	26720	207	0	0	0	0	0	0	0	26698	0	25	160100	100	80000	80000	100	80020	80016	500	1168951	1882882	0	26690	26713	26718	6636	6	6661	160136	200	80020	80024	200	80020	80020	26713	26709	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	1	0	3	0	1	1	1	5117	0	16	0	0	26710	0	0	80000	80000	100	26714	26714	26714	26714	26727
160204	26711	200	0	0	0	0	0	0	0	26699	1	25	160100	100	80000	80000	100	80027	80020	500	1168352	1884638	1	26695	26714	26913	6625	10	6650	160142	200	80023	80023	200	80023	80023	26710	26714	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	2	0	6	0	2	2	2	5127	1	24	1	1	26711	0	0	80000	80000	100	26711	26715	26715	26715	26811
160204	26723	200	0	0	0	0	12	0	0	26695	4	25	160100	100	80000	80000	100	80023	80018	500	1170734	1883607	0	26696	26710	26710	6625	10	6649	160141	200	80023	80027	200	80023	80023	26710	26714	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	5	0	3	0	2	2	2	5128	1	24	1	1	26712	0	0	80000	80000	100	26711	26715	26715	26714	26715
160204	26751	200	0	0	0	0	12	0	0	26699	2	25	160100	100	80000	80000	100	80023	80018	500	1166375	1884391	1	26695	26710	26710	6625	9	6650	160140	200	80023	80027	200	80023	80023	26714	26713	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	1	0	24	0	2	2	2	5127	1	24	1	1	26711	0	0	80000	80000	100	26715	26715	26711	26712	26715
160204	26737	200	0	0	0	0	0	0	0	26695	2	25	160100	100	80000	80000	100	80023	80018	500	1157490	1883414	1	26694	26715	26714	6625	10	6650	160141	200	80023	80027	200	80023	80023	26710	26714	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	15	0	2	2	2	5127	1	24	1	1	26711	0	0	80000	80000	100	26714	26714	26715	26715	26715
160204	26743	200	0	0	0	0	12	0	0	26700	1	25	160100	100	80000	80000	100	80023	80018	500	1188204	1883729	1	26695	26714	26713	6625	9	6649	160141	200	80023	80023	200	80023	80023	26713	26714	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	20	0	6	0	2	2	2	5128	1	24	1	1	26711	0	0	80000	80000	100	26711	26711	26715	26716	26719
160204	27221	200	0	0	0	0	12	0	0	26700	2	25	160100	100	80000	80000	100	80023	80018	500	1167786	1888163	1	26695	26714	26713	6625	9	6650	160141	200	80023	80023	200	80023	80023	26714	26714	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	30	0	6	0	2	2	2	5127	1	24	1	1	26711	0	0	80000	80000	100	26716	26730	26719	26732	26726
160204	26717	200	0	0	0	0	12	0	0	26695	0	25	160100	100	80000	80000	100	80023	80018	500	1187549	1884038	1	26695	26715	26714	6621	10	6650	160143	200	80023	80027	200	80023	80023	26713	26713	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	59	0	9	0	2	2	2	5127	1	24	1	1	26711	0	0	80000	80000	100	26715	26716	26714	26715	26715
160204	26740	200	0	0	0	0	12	0	0	26695	2	25	160100	100	80000	80000	100	80023	80018	500	1175098	1884546	0	26694	26715	26714	6621	10	6650	160140	200	80023	80023	200	80023	80023	26714	26714	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	3	0	3	0	2	2	2	5127	1	24	1	1	26711	0	0	80000	80000	100	26711	26713	26714	26711	26716

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0f	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26711	200	0	0	2	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1883869	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	17	16	17	17	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1890463	0	26690	26709	26709	6653	48	3	6689	160010	20	80000	80000	20	80189	80000	27070	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	7	17	16	16	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	199	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1885588	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	7	16	16	7	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168787	1891037	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	6	5020	16	16	7	16	26706	80000	80000	10	26710	26713	26710	26710	26710
160024	26709	200	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1887134	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	17	16	13	6	26706	80000	80000	10	26710	26710	26710	26710	26713
160024	26709	200	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1892336	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	17	16	14	6	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	1	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1892337	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26711	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	16	16	17	6	26706	80000	80000	10	26710	26713	26710	26710	26710
160024	26709	200	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1891778	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	16	16	16	16	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1899063	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	16	16	16	16	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1887615	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	6	5020	16	16	16	16	26706	80000	80000	10	26710	26710	26710	26710	26710

SCVTF (scalar, integer, S from X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations