Firestorm: SCVTF (vector, fixed-point, 2D from 2D) measurements

Code:

  scvtf v0.2d, v0.2d, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	a9	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	82	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	1	2	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->2

Code:

  scvtf v0.2d, v0.2d, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	93	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	225	3	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	225	15	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	225	3	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	225	33	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	225	33	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	225	6	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28282	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29633	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	39	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	3	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	18	0	0	103	29547	40	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	3	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	30	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	7	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	0	0	0	640	2	24	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	36	0	0	103	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	3	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	27	0	0	103	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	3	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	36	0	0	4066	29484	158	10072	13	10056	14	11050	72	4286624	0	30198	30321	30367	28316	27	28921	10916	22	10979	24	11138	30367	30356	8	1	10021	10	9	10	10	10000	10	2	0	0	2	0	19373	2	0	789	4	94	3	6	29884	0	10000	10	30356	30358	30368	30320	30369
10024	30370	227	1	1	7	7	948	616	0	5230	29475	195	10075	17	10064	16	11050	82	4286624	1	30018	30085	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	2	0	1	2	8398	2	0	724	2	65	3	4	29848	3	10000	10	30277	30320	30322	30180	30229
10024	30227	227	1	1	6	5	24	0	0	2169	29547	81	10010	10	10000	11	10450	50	4277160	0	30018	30037	30037	28319	42	28954	10913	22	11634	22	11473	30547	30510	12	1	10021	10	9	10	10	10000	10	0	0	0	1	2	30948	2	0	869	2	113	4	3	30040	2	10000	10	30511	30510	30513	30372	30510
10024	30510	228	1	1	10	3	1329	528	1	5937	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	11522	30	10978	20	10815	30180	30322	4	1	10021	10	9	10	10	10000	10	0	3	1	1	0	22355	0	0	878	4	89	3	3	30107	3	10000	10	30276	30038	30133	30038	30181
10024	30037	235	0	1	13	13	1470	88	0	8510	29430	244	10129	19	10112	17	11950	71	4292032	0	30234	30646	30037	28335	56	28897	11362	22	11482	22	11483	30508	30511	11	1	10021	10	9	10	10	10000	10	0	2	0	0	0	36415	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038

Test 3: throughput

Count: 8

Code:

  scvtf v0.2d, v8.2d, #3
  scvtf v1.2d, v8.2d, #3
  scvtf v2.2d, v8.2d, #3
  scvtf v3.2d, v8.2d, #3
  scvtf v4.2d, v8.2d, #3
  scvtf v5.2d, v8.2d, #3
  scvtf v6.2d, v8.2d, #3
  scvtf v7.2d, v8.2d, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20039	150	0	0	0	204	0	542	25	80108	100	80008	100	80020	500	640132	1	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	1	1	1	5118	16	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	3	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	1	1	1	5118	16	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	18	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	1	1	1	5118	16	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	12	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	1	1	1	5118	16	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	1	1	1	5118	16	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	27	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	1	1	1	5118	16	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	24	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	1	1	1	5118	16	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	36	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20089	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	1	1	1	5118	16	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	18	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	1	1	1	5118	16	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	12	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	1	1	1	5118	16	0	20036	0	80000	100	20040	20040	20040	20040	20040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20039	150	0	36	82	25	80010	10	80000	10	80000	50	640000	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	3	5020	11	16	4	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	82	25	80010	10	80000	10	80000	50	640000	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	1	0	3	5020	4	16	4	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	12	82	25	80010	10	80000	10	80000	50	640000	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	3	5020	4	16	4	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	12	82	25	80010	10	80000	10	80000	50	640000	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	3	5020	2	16	2	4	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	12	40	25	80010	10	80000	10	80000	50	640000	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	80204	20091	20248	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	2	16	4	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	18	82	25	80010	10	80000	10	80000	50	640000	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	1	0	3	5020	4	16	4	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	24	82	25	80010	10	80000	10	80000	50	640000	1	20020	20114	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	1	0	6	5020	4	16	3	8	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	39	82	25	80010	10	80000	10	80000	50	640000	1	20020	20039	20191	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	4	16	2	4	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	40	25	80010	10	80000	10	80000	50	640000	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	1	0	3	5020	3	16	4	4	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	155	0	0	82	25	80010	10	80000	10	80000	50	640000	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	1	2	3	5020	7	36	2	4	20036	80000	10	20040	20040	20040	20040	20040

SCVTF (vector, fixed-point, 2D from 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations