Firestorm: SCVTF (vector, fixed-point, 2S from 2S) measurements

Code:

  scvtf v0.2s, v0.2s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	61	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	1	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	6	73	1	16	1	1	2629	1000	3038	3038	3038	3086	3038
1004	3037	23	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2629	1000	3038	3061	3038	3038	3038
1004	3037	23	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	12	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	3	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	0	82	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	1	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	98	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	15	0	3	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->2

Code:

  scvtf v0.2s, v0.2s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	12	0	0	103	29547	25	10100	100	10000	100	10000	500	4278512	1	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	0	3	0	851	0	3	67	2	2	29847	22	10000	100	30370	30134	30371	30372	30326
10204	30228	227	0	0	1	7	6	825	528	2	4415	29484	156	10194	111	10048	138	11050	678	4286547	1	30090	30371	30372	28288	32	28875	11193	224	11161	226	11161	30370	30403	8	1	10201	100	99	100	100	10000	100	4	2	2	1	4	19663	2	755	0	4	73	2	2	29921	33	10000	100	30419	30182	30425	30370	30421
10204	30470	227	0	0	0	8	8	1203	704	1	5260	29474	116	10209	150	10072	152	11200	733	4287939	1	30306	30407	30468	28289	33	28873	11343	232	11161	224	11333	30469	30418	9	1	10201	100	99	100	100	10000	100	4	0	0	0	0	24890	0	763	1	1	82	3	1	29969	26	10000	100	30470	30466	30418	30465	30465
10204	30416	228	1	1	1	8	9	1065	704	2	5260	29511	175	10210	147	10072	142	11050	757	4287976	1	30342	30416	30424	28297	41	28893	11389	210	11160	232	11323	30413	30418	10	1	10201	100	99	100	100	10000	100	0	2	0	0	2	25108	2	742	0	3	106	1	3	29957	37	10000	100	30453	30466	30423	30418	30171
10204	30451	228	1	0	1	8	3	1200	704	1	5340	29466	192	10221	147	10064	147	11200	664	4287976	1	30306	30468	30465	28302	39	28913	11342	229	11164	232	11315	30416	30463	9	1	10201	100	99	100	100	10000	100	2	4	2	2	0	25233	0	710	0	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	0	0	0	710	0	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	103	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	3	0	710	0	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	12	0	0	103	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	0	3	0	710	0	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	103	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	3	0	710	0	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	12	0	0	103	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	3	0	710	0	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	3	0	640	2	16	2	2	29667	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	6	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	1	0	0	61	29547	25	10010	11	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10161	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	1	0	0	0	640	2	16	2	2	29629	2	10000	10	30038	30038	30132	30275	30275
10024	30324	228	0	0	6	7	804	528	3966	29484	150	10081	12	10048	17	11200	71	4285272	30270	30369	30368	28309	38	28914	11160	26	10985	20	11146	30132	30370	8	1	10021	10	9	10	10	10000	10	0	0	3	1	1	4	19628	4	704	2	73	3	2	29881	2	10000	10	30414	30366	30358	30418	30368
10024	30417	227	1	0	9	4	1188	704	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	22	28822	10462	20	10000	21	10982	30308	30178	2	1	10021	10	9	10	10	10000	10	2	2	0	0	0	4	22266	2	830	2	88	3	3	30068	3	10000	10	30513	30558	30512	30511	30555
10024	30417	228	1	1	10	10	1305	880	6576	29457	236	10101	18	10080	14	10450	109	4290680	30378	30561	30415	28323	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	2	0	2	0	1	0	19835	0	829	2	81	3	2	29978	3	10000	10	30512	30466	30131	30513	30419
10024	30495	228	1	0	10	7	1323	880	6579	29457	190	10107	14	10080	23	11350	61	4289328	30342	30508	30464	28314	15	28936	11216	24	10493	22	10658	30037	30037	1	1	10021	10	9	10	10	10000	10	0	2	0	0	0	4	8490	2	640	3	56	2	2	29629	0	10000	10	30038	30038	30038	30038	30038

Test 3: throughput

Count: 8

Code:

  scvtf v0.2s, v8.2s, #3
  scvtf v1.2s, v8.2s, #3
  scvtf v2.2s, v8.2s, #3
  scvtf v3.2s, v8.2s, #3
  scvtf v4.2s, v8.2s, #3
  scvtf v5.2s, v8.2s, #3
  scvtf v6.2s, v8.2s, #3
  scvtf v7.2s, v8.2s, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20061	150	0	0	72	25	80108	100	80008	100	80020	500	640132	0	20020	0	20039	20039	9977	6	9990	80120	200	80032	200	80143	20093	20039	1	1	80201	100	99	100	100	80000	100	1	12	1	1	1	5118	2	16	2	2	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	12	0	72	25	80108	100	80008	100	80020	500	640132	0	20020	0	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	1	3	1	1	1	5118	1	16	2	1	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	12	0	72	25	80108	100	80008	100	80020	500	640132	0	20020	0	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	1	3	1	1	1	5136	3	16	1	2	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	12	0	391	63	80108	100	80008	100	80020	500	640132	0	20020	0	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	1	3	1	1	1	5118	2	16	2	0	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	72	25	80108	100	80008	100	80020	500	640132	0	20020	0	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	1	3	1	1	1	5118	1	16	3	2	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	12	0	30	25	80108	100	80008	100	80020	500	640132	1	20020	0	20039	20039	9977	6	9990	80120	200	80032	200	80032	20090	20039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5118	2	16	2	1	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	12	0	72	25	80108	100	80008	100	80020	500	640132	0	20020	0	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	3	1	1	1	5118	2	16	2	2	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	114	25	80108	100	80008	100	80020	500	640132	0	20020	3	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	3	1	1	1	5118	1	16	1	2	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	12	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	0	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5118	1	16	1	2	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	12	0	30	25	80108	100	80008	100	80020	500	640132	1	20020	0	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	1	3	1	1	1	5118	2	16	1	2	20036	80000	100	20040	20040	20040	20040	20040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20051	150	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	6	16	7	17	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	230	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	17	16	17	7	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	8	16	17	8	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	17	16	6	17	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	696	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	2	0	0	5020	17	16	8	17	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	17	16	6	17	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	17	16	17	17	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	17	16	14	6	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	6	16	17	8	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	8	16	17	6	20036	80000	10	20040	20040	20040	20040	20040

SCVTF (vector, fixed-point, 2S from 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations