Firestorm: SHA1H measurements

Code:

  sha1h s0, s0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	9	61	936	25	1000	1000	1000	68921	2018	2037	2037	1787	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	936	25	1000	1000	1000	68921	2018	2037	2037	1787	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	936	25	1000	1000	1000	68921	2018	2037	2037	1787	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	936	25	1000	1000	1000	68921	2018	2037	2037	1787	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	936	25	1000	1000	1000	68921	2018	2037	2037	1787	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	936	25	1000	1000	1000	68921	2018	2037	2037	1787	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	936	25	1000	1000	1000	68921	2018	2037	2037	1787	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	936	25	1000	1000	1000	68921	2018	2037	2037	1787	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	54	61	936	25	1000	1000	1000	68921	2018	2037	2037	1787	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	936	25	1000	1000	1000	68921	2018	2037	2037	1787	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->2

Code:

  sha1h s0, s0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	0	0	0	61	9936	25	10100	100	10000	100	10000	500	707921	0	20018	20037	20037	18637	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	1	1	19968	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	9936	25	10100	100	10000	100	10000	500	707921	0	20018	20037	20037	18637	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19968	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	9936	25	10100	100	10000	100	10000	500	707921	0	20018	20037	20037	18637	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19968	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	9936	44	10100	100	10000	100	10000	500	707921	1	20018	20037	20037	18637	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19968	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	9936	25	10100	100	10000	100	10000	500	707921	0	20018	20037	20037	18637	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19968	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	9936	25	10100	100	10000	100	10000	500	707921	0	20018	20037	20037	18637	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19968	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	9936	25	10100	100	10000	100	10000	500	707921	1	20018	20037	20037	18637	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19968	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	9936	25	10100	100	10000	100	10000	500	707921	1	20018	20037	20037	18637	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19968	0	10000	100	20038	20038	20038	20038	20038
10204	20037	149	0	0	0	0	0	0	61	9936	25	10100	100	10000	100	10000	500	707921	1	20018	20037	20037	18637	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19968	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	726	9936	25	10100	100	10000	100	10000	500	707921	1	20018	20037	20037	18637	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19968	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	726	9936	25	10010	10	10000	10	10000	50	707921	20018	20037	20037	18659	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	3	16	2	2	19968	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	862	9936	25	10010	10	10000	10	10000	50	707921	20018	20037	20037	18659	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19968	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	9936	25	10010	10	10000	10	10000	50	707921	20018	20037	20037	18659	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	20004	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	9936	25	10010	10	10000	10	10000	50	707921	20018	20037	20037	18659	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19968	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	9936	25	10010	10	10000	10	10000	50	707921	20018	20037	20037	18659	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19968	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	9936	25	10010	10	10000	10	10000	50	707921	20018	20037	20037	18659	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19968	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	9936	25	10010	10	10000	10	10000	50	707921	20018	20037	20037	18659	3	18801	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19968	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	9936	25	10010	10	10000	10	10000	50	707921	20018	20037	20037	18659	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	662	2	16	2	2	19968	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	9936	25	10010	10	10000	10	10000	50	707921	20018	20037	20037	18659	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19968	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	9936	25	10010	10	10000	10	10000	50	707921	20018	20037	20037	18659	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19968	10000	10	20038	20038	20038	20038	20038

Test 3: throughput

Count: 8

Code:

  sha1h s0, s8
  sha1h s1, s8
  sha1h s2, s8
  sha1h s3, s8
  sha1h s4, s8
  sha1h s5, s8
  sha1h s6, s8
  sha1h s7, s8

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80040	600	0	0	0	0	0	0	192	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	69971	6	69992	80100	200	80008	200	80008	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	3	0	1	1	1	5117	0	16	0	0	80035	80000	100	80039	80039	80039	80039	80039
80204	80038	599	0	0	0	0	0	0	38	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80086	70010	6	69992	80100	200	80008	200	80008	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	1	0	0	0	1	1	1	5117	0	16	0	0	80035	80000	100	80039	80039	80039	80039	80039
80204	80038	600	0	0	0	0	0	0	1134	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	69971	6	69992	80125	200	80008	200	80008	80038	80038	1	1	80201	100	99	100	100	80000	100	2	0	0	0	0	0	1	1	1	5117	0	16	0	0	80072	80000	100	80039	80039	80039	80184	80039
80204	80038	600	0	0	0	0	0	0	250	44	80100	100	80000	100	80000	500	640000	0	80019	80038	80038	69971	6	69992	80100	200	80008	200	80008	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	1	1	1	5117	0	49	0	0	80035	80000	100	80039	80039	80039	80039	80039
80204	80038	600	0	0	0	0	0	0	208	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	69971	6	69992	80100	200	80008	200	80008	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	1	1	1	5117	0	16	0	0	80035	80000	100	80039	80039	80039	80039	80039
80204	80038	599	0	0	0	0	0	0	208	25	80100	100	80000	100	80000	500	640780	0	80019	80038	80038	69971	6	69992	80100	200	80008	200	80008	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	3	0	1	1	1	5117	0	16	0	0	80035	80000	100	80039	80039	80039	80039	80039
80204	80038	600	0	0	0	0	0	0	59	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	69971	6	69992	80100	200	80008	200	80008	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	1	1	1	5117	0	16	0	0	80183	80000	100	80039	80039	80039	80039	80039
80204	80038	600	0	0	0	0	0	0	38	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	69971	6	69992	80100	200	80008	200	80008	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	1	1	1	5117	0	16	0	0	80183	80000	100	80039	80039	80039	80039	80039
80204	80038	600	0	0	0	0	0	0	38	44	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	69971	6	69992	80100	200	80008	200	80008	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	3	0	1	1	1	5117	1	16	0	0	80035	80000	100	80039	80039	80039	80039	80039
80204	80038	600	0	0	0	0	0	0	38	25	80100	100	80000	100	80000	500	640000	0	80019	80038	80038	69971	6	69992	80100	200	80008	200	80008	80038	80038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	1	1	1	5117	0	16	0	0	80035	80000	100	80039	80039	80039	80233	80039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80039	600	60	49	25	80010	10	80000	10	80000	50	640000	1	80019	0	80038	80038	69986	3	70018	80010	20	80000	20	80000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	7	16	2	4	80033	0	80000	10	80039	80039	80039	80039	80039
80025	80038	599	0	49	25	80010	10	80000	10	80000	50	640000	0	80019	0	80038	80038	69986	3	70018	80010	20	80000	20	80000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	4	16	6	4	80033	0	80000	10	80039	80039	80039	80039	80039
80024	80038	599	0	714	25	80010	10	80000	10	80000	50	640000	0	80019	0	80038	80038	69986	3	70018	80010	20	80000	20	80000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	4	16	4	2	80033	0	80000	10	80039	80039	80039	80039	80039
80024	80038	599	39	49	25	80010	10	80000	10	80000	50	640000	0	80019	0	80038	80038	69986	3	70018	80010	20	80000	20	80000	80038	80038	1	1	80021	10	9	10	10	80000	10	3	3	0	0	5020	4	16	4	5	80033	0	80000	10	80039	80039	80039	80039	80039
80024	80038	600	0	49	25	80010	10	80000	10	80000	50	640000	0	80019	0	80038	80038	69986	3	70018	80010	20	80000	20	80000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	4	16	4	4	80033	0	80000	10	80039	80039	80039	80039	80039
80024	80038	600	0	353	25	80010	10	80000	10	80000	50	640000	0	80019	0	80038	80038	69986	3	70018	80010	20	80917	20	80381	80957	80426	19	1	80021	10	9	10	10	80000	10	0	1063	0	0	5020	2	16	4	2	80033	0	80000	10	80039	80039	80039	80039	80039
80024	80038	599	66	137	25	80102	10	80000	10	80000	50	640000	0	80019	0	80038	80230	69986	3	70018	80010	20	80000	20	80000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	3	0	0	5020	4	16	7	2	80033	0	80000	10	80039	80039	80039	80039	80136
80024	80038	599	39	49	25	80033	10	80000	10	80000	50	640000	0	80019	0	80038	80038	69986	3	70054	80010	20	80000	20	80000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	0	0	1	5020	2	16	4	2	80033	0	80000	10	80039	80039	80039	80039	80039
80024	80038	599	0	49	25	80010	10	80000	10	80000	50	640000	0	80019	0	80038	80038	69986	3	70018	80010	20	80000	20	80000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	4	16	4	2	80033	0	80000	10	80039	80039	80039	80039	80039
80024	80038	600	0	49	25	80010	10	80000	10	80000	50	640000	0	80019	0	80038	80038	69986	3	70018	80010	20	80000	20	80000	80038	80038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	2	16	2	4	80033	0	80000	10	80087	80039	80039	80039	80039

SHA1H

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations