Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SHA1H

Test 1: uops

Code:

  sha1h s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715961936251000100010006892120182037203717873189510001000100020372037111001100000073116111969100020382038203820382038
1004203715061936251000100010006892120182037203717873189510001000100020372037111001100000073116111969100020382038203820382038
1004203715061936251000100010006892120182037203717873189510001000100020372037111001100000073116111969100020382038203820382038
1004203715061936251000100010006892120182037203717873189510001000100020372037111001100000073116111969100020382038203820382038
1004203715061936251000100010006892120182037203717873189510001000100020372037111001100000073116111969100020382038203820382038
1004203716061936251000100010006892120182037203717873189510001000100020372037111001100000073116111969100020382038203820382038
1004203715061936251000100010006892120182037203717873189510001000100020372037111001100000073116111969100020382038203820382038
1004203715061936251000100010006892120182037203717873189510001000100020372037111001100000073116111969100020382038203820382038
10042037155461936251000100010006892120182037203717873189510001000100020372037111001100000073116111969100020382038203820382038
1004203715061936251000100010006892120182037203717873189510001000100020372037111001100000073116111969100020382038203820382038

Test 2: Latency 1->2

Code:

  sha1h s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000000619936251010010010000100100005007079210200182003720037186373187451010020010000200100002003720037111020110099100100100001000000071021611199680100001002003820038200382003820038
1020420037150000000619936251010010010000100100005007079210200182003720037186373187451010020010000200100002003720037111020110099100100100001000000071011611199680100001002003820038200382003820038
1020420037150000000619936251010010010000100100005007079210200182003720037186373187451010020010000200100002003720037111020110099100100100001000000071011611199680100001002003820038200382003820038
1020420037150000000619936441010010010000100100005007079211200182003720037186373187451010020010000200100002003720037111020110099100100100001000000071011611199680100001002003820038200382003820038
1020420037150000000619936251010010010000100100005007079210200182003720037186373187451010020010000200100002003720037111020110099100100100001000000071011611199680100001002003820038200382003820038
1020420037150000000619936251010010010000100100005007079210200182003720037186373187451010020010000200100002003720037111020110099100100100001000000071011611199680100001002003820038200382003820038
1020420037150000000619936251010010010000100100005007079211200182003720037186373187451010020010000200100002003720037111020110099100100100001000000071011611199680100001002003820038200382003820038
1020420037150000000619936251010010010000100100005007079211200182003720037186373187451010020010000200100002003720037111020110099100100100001000000071011611199680100001002003820038200382003820038
1020420037149000000619936251010010010000100100005007079211200182003720037186373187451010020010000200100002003720037111020110099100100100001000000071011611199680100001002003820038200382003820038
10204200371500000007269936251010010010000100100005007079211200182003720037186373187451010020010000200100002003720037111020110099100100100001000000071011611199680100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000007269936251001010100001010000507079212001820037200371865931876710010201000020100002003720037111002110910101000010000000640316221996810000102003820038200382003820038
100242003715000008629936251001010100001010000507079212001820037200371865931876710010201000020100002003720037111002110910101000010000000640216221996810000102003820038200382003820038
10024200371500000619936251001010100001010000507079212001820037200371865931876710010201000020100002003720037111002110910101000010000000640216222000410000102003820038200382003820038
10024200371500000619936251001010100001010000507079212001820037200371865931876710010201000020100002003720037111002110910101000010000000640216221996810000102003820038200382003820038
10024200371500000619936251001010100001010000507079212001820037200371865931876710010201000020100002003720037111002110910101000010000000640216221996810000102003820038200382003820038
10024200371500000619936251001010100001010000507079212001820037200371865931876710010201000020100002003720037111002110910101000010000000640216221996810000102003820038200382003820038
10024200371500000619936251001010100001010000507079212001820037200371865931880110010201000020100002003720037111002110910101000010000000640216221996810000102003820038200382003820038
10024200371500000619936251001010100001010000507079212001820037200371865931876710010201000020100002003720037111002110910101000010000000662216221996810000102003820038200382003820038
10024200371500000619936251001010100001010000507079212001820037200371865931876710010201000020100002003720037111002110910101000010000000640216221996810000102003820038200382003820038
10024200371500000619936251001010100001010000507079212001820037200371865931876710010201000020100002003720037111002110910101000010000000640216221996810000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  sha1h s0, s8
  sha1h s1, s8
  sha1h s2, s8
  sha1h s3, s8
  sha1h s4, s8
  sha1h s5, s8
  sha1h s6, s8
  sha1h s7, s8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204800406000000001922580100100800001008000050064000018001980038800386997166999280100200800082008000880038800381180201100991001008000010000003011151170160080035800001008003980039800398003980039
8020480038599000000382580100100800001008000050064000018001980038800867001066999280100200800082008000880038800381180201100991001008000010000100011151170160080035800001008003980039800398003980039
802048003860000000011342580100100800001008000050064000018001980038800386997166999280125200800082008000880038800381180201100991001008000010020000011151170160080072800001008003980039800398018480039
80204800386000000002504480100100800001008000050064000008001980038800386997166999280100200800082008000880038800381180201100991001008000010000000011151170490080035800001008003980039800398003980039
80204800386000000002082580100100800001008000050064000018001980038800386997166999280100200800082008000880038800381180201100991001008000010000000011151170160080035800001008003980039800398003980039
80204800385990000002082580100100800001008000050064078008001980038800386997166999280100200800082008000880038800381180201100991001008000010000003011151170160080035800001008003980039800398003980039
8020480038600000000592580100100800001008000050064000018001980038800386997166999280100200800082008000880038800381180201100991001008000010000000011151170160080183800001008003980039800398003980039
8020480038600000000382580100100800001008000050064000018001980038800386997166999280100200800082008000880038800381180201100991001008000010000000011151170160080183800001008003980039800398003980039
8020480038600000000384480100100800001008000050064000018001980038800386997166999280100200800082008000880038800381180201100991001008000010000003011151171160080035800001008003980039800398003980039
8020480038600000000382580100100800001008000050064000008001980038800386997166999280100200800082008000880038800381180201100991001008000010000000011151170160080035800001008003980039800398023380039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002480039600604925800101080000108000050640000180019080038800386998637001880010208000020800008003880038118002110910108000010000050207162480033080000108003980039800398003980039
800258003859904925800101080000108000050640000080019080038800386998637001880010208000020800008003880038118002110910108000010000050204166480033080000108003980039800398003980039
8002480038599071425800101080000108000050640000080019080038800386998637001880010208000020800008003880038118002110910108000010000050204164280033080000108003980039800398003980039
8002480038599394925800101080000108000050640000080019080038800386998637001880010208000020800008003880038118002110910108000010330050204164580033080000108003980039800398003980039
800248003860004925800101080000108000050640000080019080038800386998637001880010208000020800008003880038118002110910108000010000050204164480033080000108003980039800398003980039
80024800386000353258001010800001080000506400000800190800388003869986370018800102080917208038180957804261918002110910108000010010630050202164280033080000108003980039800398003980039
80024800385996613725801021080000108000050640000080019080038802306998637001880010208000020800008003880038118002110910108000010030050204167280033080000108003980039800398003980136
8002480038599394925800331080000108000050640000080019080038800386998637005480010208000020800008003880038118002110910108000010000150202164280033080000108003980039800398003980039
800248003859904925800101080000108000050640000080019080038800386998637001880010208000020800008003880038118002110910108000010000050204164280033080000108003980039800398003980039
800248003860004925800101080000108000050640000080019080038800386998637001880010208000020800008003880038118002110910108000010000050202162480033080000108008780039800398003980039