Firestorm: SHA1SU0 measurements

Code:

  sha1su0 v0.4s, v1.4s, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	16	0	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	0	73	2	16	2	2	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	0	73	2	16	2	2	1969	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	0	73	2	16	2	2	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	21	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	0	73	2	16	2	2	1969	1000	2038	2038	2038	2038	2038
1004	2037	17	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1056	3000	2037	2037	1	1	1001	1000	0	0	0	73	2	16	2	2	2032	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1044	1000	3000	2037	2037	1	1	1001	1000	0	0	0	73	2	16	2	2	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	0	73	2	16	2	2	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	0	73	2	16	2	2	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	0	73	2	16	2	2	1969	1000	2038	2038	2038	2038	2038
1004	2037	16	15	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	0	73	2	16	2	2	1969	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  sha1su0 v0.4s, v1.4s, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	103	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	3	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	815	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	9	0	796	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20085	4	1	10201	100	99	100	100	10000	100	0	0	710	0	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	172	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	550	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	130	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	156	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	3	710	1	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	0	170	9937	25	10010	10	10000	10	10000	50	707984	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	9918	25	10010	10	10000	10	10000	50	707984	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	103	9937	25	10010	10	10000	10	10000	50	707984	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	3	19969	10000	10	20038	20086	20038	20038	20038
10024	20037	149	0	0	0	0	0	103	9937	25	10010	10	10000	10	10000	50	707984	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20084	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	724	9937	25	10010	10	10000	10	10000	50	707984	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	3	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	749	9937	25	10010	10	10000	10	10000	50	707984	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	519	9937	25	10010	10	10000	10	10000	50	707984	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	3	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	82	9937	25	10010	10	10000	10	10000	50	707984	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  sha1su0 v0.4s, v0.4s, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	0	0	0	0	214	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	212	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	60	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19967	0	10000	100	20038	20038	20225	20038	20038
10204	20037	150	0	0	0	0	0	0	0	145	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10055	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	145	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	712	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	103	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	124	9918	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	536	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	20076	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	189	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038

Test 4: Latency 1->3

Code:

  sha1su0 v0.4s, v1.4s, v0.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	0	0	0	0	166	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18744	10125	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	3	17	2	2	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	1	229	9937	25	10100	100	10000	100	10000	500	707984	1	20018	20037	20037	18638	3	18744	10125	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	9937	25	10125	100	10000	100	10000	500	707984	1	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	1	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	17	1	2	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	1	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	20005	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	124	9937	25	10125	125	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	1	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	19967	25	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	4	16	5	5	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	6	16	5	6	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	6	16	6	4	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	6	16	5	6	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	5	16	6	6	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	6	16	6	4	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	5	16	6	4	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	5	16	4	4	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	6	16	5	6	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	6	16	5	6	19969	10000	10	20038	20038	20038	20038	20038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sha1su0 v0.4s, v8.4s, v9.4s
  movi v1.16b, 0
  sha1su0 v1.4s, v8.4s, v9.4s
  movi v2.16b, 0
  sha1su0 v2.4s, v8.4s, v9.4s
  movi v3.16b, 0
  sha1su0 v3.4s, v8.4s, v9.4s
  movi v4.16b, 0
  sha1su0 v4.4s, v8.4s, v9.4s
  movi v5.16b, 0
  sha1su0 v5.4s, v8.4s, v9.4s
  movi v6.16b, 0
  sha1su0 v6.4s, v8.4s, v9.4s
  movi v7.16b, 0
  sha1su0 v7.4s, v8.4s, v9.4s

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160205	80038	600	0	0	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	0	80019	80038	80038	59964	3	59996	80100	200	80000	200	240000	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	599	0	0	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	0	80019	80038	80038	59964	3	59996	80100	200	80000	200	240000	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	599	0	0	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	0	80019	80038	80038	59964	3	59996	80100	200	80000	200	240000	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	600	0	0	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	0	80019	80038	80038	59964	3	59996	80100	200	80000	200	240000	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	600	0	0	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	0	80019	80038	80038	59964	3	59996	80100	200	80000	200	240000	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	0	0	10110	1	16	1	1	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	600	0	0	0	0	0	0	714	25	80100	100	80000	100	80000	500	640000	0	80019	80038	80038	59964	3	59996	80100	200	80000	200	240000	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	599	0	0	0	0	0	0	714	25	80100	100	80000	100	80000	500	640000	0	80019	80038	80038	59964	3	59996	80100	200	80000	200	240000	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	600	0	0	0	0	0	0	49	25	80123	100	80000	100	80000	500	640000	0	80019	80038	80038	59964	3	59996	80100	200	80000	200	240000	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	3	0	0	0	0	10110	1	16	1	1	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	599	0	0	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	0	80019	80038	80038	59964	3	59996	80100	200	80000	200	240000	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	599	0	0	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	0	80019	80038	80038	59964	3	59996	80100	200	80000	200	240000	80038	80086	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	1	16	2	1	80035	0	160000	100	80039	80039	80039	80039	80039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	80038	600	0	0	0	0	0	0	0	0	55	25	80010	10	80000	10	80000	50	640000	1	1	5	80019	80038	80038	59986	3	60018	80010	20	80000	20	240000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	8	2	1	21	56	2	2	1	21	16	80035	0	40	13	160000	10	80039	80039	80039	80039	80039
160024	80038	599	0	0	0	0	0	0	0	0	55	25	80010	10	80000	10	80000	50	640000	1	1	5	80019	80038	80038	59986	3	60018	80010	20	80000	20	240000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	8	2	1	14	16	2	1	1	13	14	80035	0	20	13	160000	10	80039	80039	80039	80039	80039
160024	80038	599	0	0	0	0	0	0	0	0	55	25	80010	10	80000	10	80000	50	640000	1	1	5	80019	80038	80038	59986	3	60018	80010	20	80000	20	240000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	3	10024	8	2	1	14	16	2	1	1	15	14	80035	0	20	13	160000	10	80039	80039	80039	80039	80039
160024	80038	600	0	0	0	0	0	0	0	0	55	25	80010	10	80000	10	80000	50	640000	1	1	5	80019	80038	80038	59986	3	60018	80010	20	80000	20	240000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	8	3	1	12	16	2	1	1	14	13	80035	0	40	13	160000	10	80039	80039	80039	80039	80039
160024	80038	599	1	0	0	0	0	45	0	0	55	25	80010	10	80000	10	80000	50	640000	1	1	5	80019	80231	80038	59986	3	60018	80010	20	80000	20	240000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	8	2	2	16	16	2	1	1	13	13	80035	0	20	13	160000	10	80039	80039	80039	80039	80039
160024	80136	599	0	0	0	0	0	0	0	0	55	25	80010	10	80000	10	80000	50	640000	1	1	5	80019	80038	80038	59986	3	60018	80010	20	80000	20	240000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	11	2	1	13	16	2	2	1	9	15	80035	0	20	13	160000	10	80039	80039	80087	80039	80039
160024	80038	600	0	0	0	0	0	0	0	0	720	25	80010	10	80000	10	80000	50	640000	1	1	5	80019	80038	80038	59986	3	60018	80010	20	80000	20	240201	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	8	2	1	13	16	2	1	1	8	16	80035	0	20	13	160000	10	80039	80039	80039	80039	80039
160024	80038	600	0	0	0	0	0	0	0	0	55	25	80010	10	80000	10	80000	50	640000	1	1	5	80019	80038	80038	59986	3	60018	80010	20	80000	20	240000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	8	2	1	14	16	2	1	1	14	14	80035	0	20	13	160000	10	80039	80039	80039	80039	80039
160024	80038	600	0	0	0	0	0	0	0	0	61	25	80010	10	80000	10	80000	50	640000	1	1	5	80019	80038	80038	59986	3	60018	80010	20	80000	20	240000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	8	3	1	15	16	2	1	2	15	13	80035	1	40	26	160000	10	80039	80039	80184	80039	80039
160024	80038	600	0	0	0	0	0	0	0	0	1129	25	80010	10	80000	10	80000	50	640000	1	1	5	80019	80038	80038	59986	3	60018	80010	20	80000	20	240000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	11	2	2	14	24	2	1	1	14	13	80035	0	20	13	160000	10	80039	80039	80039	80039	80039

Test 6: throughput

Count: 16

Code:

  sha1su0 v0.4s, v16.4s, v17.4s
  sha1su0 v1.4s, v16.4s, v17.4s
  sha1su0 v2.4s, v16.4s, v17.4s
  sha1su0 v3.4s, v16.4s, v17.4s
  sha1su0 v4.4s, v16.4s, v17.4s
  sha1su0 v5.4s, v16.4s, v17.4s
  sha1su0 v6.4s, v16.4s, v17.4s
  sha1su0 v7.4s, v16.4s, v17.4s
  sha1su0 v8.4s, v16.4s, v17.4s
  sha1su0 v9.4s, v16.4s, v17.4s
  sha1su0 v10.4s, v16.4s, v17.4s
  sha1su0 v11.4s, v16.4s, v17.4s
  sha1su0 v12.4s, v16.4s, v17.4s
  sha1su0 v13.4s, v16.4s, v17.4s
  sha1su0 v14.4s, v16.4s, v17.4s
  sha1su0 v15.4s, v16.4s, v17.4s

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0002

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	160040	1198	0	0	0	0	0	0	189	49	25	160100	100	160000	100	160000	500	1280000	160019	160038	160038	139964	0	3	139996	160100	200	160000	200	480000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	2	16	2	2	160035	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	0	0	48	49	25	160100	100	160000	100	160000	500	1280000	160019	160038	160038	139964	0	3	139996	160100	200	160000	200	480000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	3645	0	0	10110	2	16	2	2	160035	0	160000	100	160039	160088	160039	160039	160039
160204	160038	1199	0	0	0	0	0	0	9	49	25	160100	100	160000	100	160000	500	1280000	160019	160038	160038	139964	0	3	139996	160100	200	160000	200	480000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	2	16	2	2	160035	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	1	1	0	49	25	160100	100	160000	100	160000	500	1280000	160019	160038	160038	139964	0	3	140034	160100	200	160000	200	480000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	2	0	3	0	0	10110	2	16	2	2	160035	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	0	0	0	49	25	160100	100	160000	100	160000	500	1280000	160019	160038	160038	139964	0	3	139996	160100	200	160000	200	480000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	2	16	2	2	160035	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	0	0	135	49	25	160100	100	160000	100	160000	500	1280000	160019	160038	160038	139964	0	3	139996	160100	200	160000	200	480000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	2	16	2	2	160035	0	160000	100	160039	160039	160039	160039	160085
160204	160038	1199	0	0	0	0	0	0	39	49	25	160100	100	160000	100	160000	500	1280000	160019	160038	160038	139964	0	3	139996	160100	200	160000	200	480144	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	2	16	2	3	160035	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	0	0	0	49	25	160100	114	160000	100	160000	500	1280000	160019	160038	160038	139964	0	3	139996	160100	200	160000	200	480000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	2	16	2	2	160035	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	0	0	75	714	25	160100	100	160000	100	160000	500	1280000	160019	160038	160038	139964	0	3	139996	160100	200	160000	200	480000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	2	16	2	2	160035	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	0	0	51	49	25	160100	100	160000	100	160000	500	1280000	160019	160038	160038	139964	3	3	139996	160100	200	160000	200	480000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	10110	2	16	2	2	160035	0	160000	100	160039	160039	160039	160039	160039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0002

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	160087	1199	1	1	0	0	6	0	76	25	160010	10	160000	10	160000	50	1280000	1	1	5	160019	160038	160038	139986	0	3	140018	160010	20	160000	20	480000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10022	7	1	1	8	16	2	1	1	4	5	160033	0	20	16	0	160000	10	160039	160039	160087	160039	160039
160024	160038	1199	0	0	0	0	0	0	55	25	160010	10	160000	10	160000	50	1280000	1	1	5	160019	160038	160038	139986	0	3	140018	160010	20	160000	20	480000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10022	8	5	2	7	16	2	2	1	5	3	160033	0	20	16	0	160000	10	160039	160039	160039	160039	160039
160024	160038	1198	0	0	0	0	0	1	103	25	160010	10	160000	10	160000	50	1280000	1	1	5	160019	160038	160038	139986	0	3	140018	160010	20	160000	20	480000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	3	0	0	0	0	0	0	0	10022	8	5	1	4	16	2	1	1	7	7	160033	0	20	16	0	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	0	0	0	0	0	61	25	160010	10	160000	10	160000	50	1280000	1	1	5	160019	160038	160038	139986	0	26	140006	160010	20	160000	20	480000	160038	160038	1	1	160022	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10022	8	5	1	5	16	2	1	1	3	6	160033	0	20	16	0	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	0	0	0	0	0	55	25	160010	10	160000	10	160000	50	1280000	1	1	5	160019	160038	160038	139986	0	3	140018	160010	20	160000	20	480000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10022	8	5	1	7	16	2	1	1	4	8	160033	0	20	16	0	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	0	0	0	0	0	226	25	160010	10	160000	10	160000	50	1280000	1	1	5	160019	160038	160038	139986	0	3	140018	160010	20	160000	20	480000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10040	8	1	1	3	16	2	1	1	8	7	160033	0	20	16	0	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	0	0	0	0	0	55	25	160010	10	160000	10	160000	50	1280000	1	1	5	160019	160038	160038	139986	0	3	140018	160010	20	160000	20	480000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10022	8	5	1	8	16	2	1	1	8	8	160033	0	20	16	0	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	0	0	0	702	0	55	25	160010	10	160000	10	160000	50	1280195	1	1	5	160019	160038	160038	139986	0	3	140018	160010	20	160000	20	480000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10022	8	5	1	7	16	2	1	1	7	7	160033	0	20	16	0	160000	10	160039	160039	160039	160039	160085
160024	160038	1198	0	0	0	0	0	0	55	25	160010	10	160000	10	160000	50	1280195	1	1	5	160019	160038	160038	139986	0	3	140018	160010	20	160000	20	480000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10022	3	5	1	7	16	2	1	1	5	8	160033	0	20	16	0	160000	10	160039	160039	160039	160039	160039
160024	160038	1198	0	0	0	0	0	0	55	25	160010	10	160000	10	160000	50	1280000	1	0	0	160019	160038	160038	139986	0	3	140018	160010	20	160000	20	480000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10022	8	5	1	6	16	2	17	1	6	7	160033	0	20	16	0	160000	10	160039	160039	160039	160039	160039

SHA1SU0

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations