Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SHA1SU0

Test 1: uops

Code:

  sha1su0 v0.4s, v1.4s, v2.4s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037160619372510001000100068984120182037203717883189510001000300020372037111001100000073216221969100020382038203820382038
10042037150619372510001000100068984020182037203717883189510001000300020372037111001100000073216221969100020382038203820382038
10042037160619372510001000100068984120182037203717883189510001000300020372037111001100000073216221969100020382038203820382038
100420371521619372510001000100068984020182037203717883189510001000300020372037111001100000073216221969100020382038203820382038
10042037170619372510001000100068984020182037203717883189510001056300020372037111001100000073216222032100020382038203820382038
10042037160619372510001000100068984020182037203717883189510441000300020372037111001100000073216221969100020382038203820382038
10042037150619372510001000100068984020182037203717883189510001000300020372037111001100000073216221969100020382038203820382038
10042037150619372510001000100068984020182037203717883189510001000300020372037111001100000073216221969100020382038203820382038
10042037150619372510001000100068984020182037203717883189510001000300020372037111001100000073216221969100020382038203820382038
100420371615619372510001000100068984120182037203717883189510001000300020372037111001100000073216221969100020382038203820382038

Test 2: Latency 1->1

Code:

  sha1su0 v0.4s, v1.4s, v2.4s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000103993725101001001000010010000500707984200182003720037186383187451010020010000200300002003720037111020110099100100100001000071003162219967100001002003820038200382003820038
1020420037150000815993725101001001000010010000500707984200182003720037186383187451010020010000200300002003720037111020110099100100100001000071002162219967100001002003820038200382003820038
102042003715000061993725101001001000010010000500707984200182003720037186383187451010020010000200300002003720037111020110099100100100001000071002162219967100001002003820038200382003820038
1020420037150090796993725101001001000010010000500707984200182003720037186383187451010020010000200300002003720085411020110099100100100001000071002162219967100001002003820038200382003820038
1020420037150000172993725101001001000010010000500707984200182003720037186383187451010020010000200300002003720037111020110099100100100001000071012162219967100001002003820038200382003820038
1020420037150000550993725101001001000010010000500707984200182003720037186383187451010020010000200300002003720037111020110099100100100001000071012162219967100001002003820038200382003820038
102042003715000061993725101001001000010010000500707984200182003720037186383187451010020010000200300002003720037111020110099100100100001000071012162219967100001002003820038200382003820038
1020420037150000130993725101001001000010010000500707984200182003720037186383187451010020010000200300002003720037111020110099100100100001000071012162219967100001002003820038200382003820038
102042003715600061993725101001001000010010000500707984200182003720037186383187451010020010000200300002003720037111020110099100100100001000071012162219967100001002003820038200382003820038
102042003715000061993725101001001000010010000500707984200182003720037186383187451010020010000200300002003720037111020110099100100100001000371012162219967100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000000170993725100101010000101000050707984200182003720037186603187671001020100002030000200372003711100211091010100001000000640216221996910000102003820038200382003820038
10024200371500000061993725100101010000101000050707984200182003720037186603187671001020100002030000200372003711100211091010100001000000640216221996910000102003820038200382003820038
10024200371500000061991825100101010000101000050707984200182003720037186603187671001020100002030000200372003711100211091010100001000000640216221996910000102003820038200382003820038
100242003715000000103993725100101010000101000050707984200182003720037186603187671001020100002030000200372003711100211091010100001000000640216231996910000102003820086200382003820038
100242003714900000103993725100101010000101000050707984200182003720037186603187671001020100002030000200842003711100211091010100001000000640216221996910000102003820038200382003820038
100242003715000000724993725100101010000101000050707984200182003720037186603187671001020100002030000200372003711100211091010100001000000640216221996910000102003820038200382003820038
10024200371500000061993725100101010000101000050707984200182003720037186603187671001020100002030000200372003711100211091010100001000000640216231996910000102003820038200382003820038
100242003715000000749993725100101010000101000050707984200182003720037186603187671001020100002030000200372003711100211091010100001000000640216221996910000102003820038200382003820038
100242003715000000519993725100101010000101000050707984200182003720037186603187671001020100002030000200372003711100211091010100001000000640216321996910000102003820038200382003820038
10024200371500000082993725100101010000101000050707984200182003720037186603187671001020100002030000200372003711100211091010100001000000640216221996910000102003820038200382003820038

Test 3: Latency 1->2

Code:

  sha1su0 v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000000021499372510100100100001001000050070798420018200372003718638318745101002001000020030000200372003711102011009910010010000100000000071011611199670100001002003820038200382003820038
1020420037150000000021299372510100100100001001000050070798420018200372003718638318745101002001000020030000200372003711102011009910010010000100000000071011611199670100001002003820038200382003820038
102042003715000000006199372510100100100001001000050070798420018200372003718638318745101002001000020030000200372003711102011009910010010000100000000071011611199670100001002003820038200382003820038
1020420037150000060006199372510100100100001001000050070798420018200372003718638318745101002001000020030000200372003711102011009910010010000100000000071011611199670100001002003820038200382003820038
102042003715000000006199372510100100100001001000050070798420018200372003718638318745101002001000020030000200372003711102011009910010010000100000000071011611199670100001002003820038200382003820038
102042003715000000006199372510100100100001001000050070798420018200372003718638318745101002001000020030000200372003711102011009910010010000100000000071011611199670100001002003820038202252003820038
1020420037150000000014599372510100100100001001000050070798420018200372003718638318745101002001005520030000200372003711102011009910010010000100000000071011611199670100001002003820038200382003820038
102042003715000000006199372510100100100001001000050070798420018200372003718638318745101002001000020030000200372003711102011009910010010000100000000071011611199670100001002003820038200382003820038
1020420037150000000014599372510100100100001001000050070798420018200372003718638318745101002001000020030000200372003711102011009910010010000100000000071011611199670100001002003820038200382003820038
102042003715000000006199372510100100100001001000050070798420018200372003718638318745101002001000020030000200372003711102011009910010010000100000000071211611199670100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715001039937251001010100001010000507079840200182003720037186603187671001020100002030000200372003711100211091010100001000640216221996910000102003820038200382003820038
10024200371500619937251001010100001010000507079840200182003720037186603187671001020100002030000200372003711100211091010100001000640216221996910000102003820038200382003820038
100242003715001249918251001010100001010000507079840200182003720037186603187671001020100002030000200372003711100211091010100001000640216221996910000102003820038200382003820038
10024200371500619937251001010100001010000507079840200182003720037186603187671001020100002030000200372003711100211091010100001000640216221996910000102003820038200382003820038
10024200371500619937251001010100001010000507079840200182003720037186603187671001020100002030000200372003711100211091010100001000640216221996910000102003820038200382003820038
10024200371500619937251001010100001010000507079840200182003720037186603187671001020100002030000200372003711100211091010100001000640216221996910000102003820038200382003820038
100242003715005369937251001010100001010000507079840200182003720037186603187671001020100002030000200372003711100211091010100001000640216222007610000102003820038200382003820038
100242003715001899937251001010100001010000507079840200182003720037186603187671001020100002030000200372003711100211091010100001000640216221996910000102003820038200382003820038
10024200371500619937251001010100001010000507079840200182003720037186603187671001020100002030000200372003711100211091010100001000640216221996910000102003820038200382003820038
10024200371500619937251001010100001010000507079840200182003720037186603187671001020100002030000200372003711100211091010100001000640216221996910000102003820038200382003820038

Test 4: Latency 1->3

Code:

  sha1su0 v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000000016699372510100100100001001000050070798402001820037200371863831874410125200100002003000020037200371110201100991001001000010000000071031722199670100001002003820038200382003820038
102042003715000000006199372510100100100001001000050070798402001820037200371863831874510100200100002003000020037200371110201100991001001000010000000071011611199670100001002003820038200382003820038
102042003715000000006199372510100100100001001000050070798402001820037200371863831874510100200100002003000020037200371110201100991001001000010000000071011611199670100001002003820038200382003820038
1020420037150000000122999372510100100100001001000050070798412001820037200371863831874410125200100002003000020037200371110201100991001001000010000000071011611199670100001002003820038200382003820038
102042003715000000006199372510125100100001001000050070798412001820037200371863831874510100200100002003000020037200371110201100991001001000010000000071011611199670100001002003820038200382003820038
102042003715000000006199372510100100100001001000050070798412001820037200371863831874510100200100002003000020037200371110201100991001001000010000000071011712199670100001002003820038200382003820038
102042003715000000006199372510100100100001001000050070798402001820037200371863831874510100200100002003000020037200371110201100991001001000010000000071011611199670100001002003820038200382003820038
102042003715000000006199372510100100100001001000050070798412001820037200371863831874510100200100002003000020037200371110201100991001001000010000000071011611200050100001002003820038200382003820038
1020420037150000000012499372510125125100001001000050070798402001820037200371863831874510100200100002003000020037200371110201100991001001000010000000071011611199670100001002003820038200382003820038
1020420037150000000061993725101001001000010010000500707984120018200372003718638318745101002001000020030000200372003711102011009910010010000100000000710116111996725100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000619937251001010100001010000507079840200182003720037186603187671001020100002030000200372003711100211091010100001000640416551996910000102003820038200382003820038
1002420037150000619937251001010100001010000507079840200182003720037186603187671001020100002030000200372003711100211091010100001000640616561996910000102003820038200382003820038
1002420037150000619937251001010100001010000507079840200182003720037186603187671001020100002030000200372003711100211091010100001000640616641996910000102003820038200382003820038
1002420037150000619937251001010100001010000507079840200182003720037186603187671001020100002030000200372003711100211091010100001000640616561996910000102003820038200382003820038
1002420037150000619937251001010100001010000507079840200182003720037186603187671001020100002030000200372003711100211091010100001000640516661996910000102003820038200382003820038
1002420037150000619937251001010100001010000507079841200182003720037186603187671001020100002030000200372003711100211091010100001000640616641996910000102003820038200382003820038
1002420037150000619937251001010100001010000507079840200182003720037186603187671001020100002030000200372003711100211091010100001000640516641996910000102003820038200382003820038
1002420037150000619937251001010100001010000507079840200182003720037186603187671001020100002030000200372003711100211091010100001000640516441996910000102003820038200382003820038
1002420037150000619937251001010100001010000507079840200182003720037186603187671001020100002030000200372003711100211091010100001000640616561996910000102003820038200382003820038
1002420037150000619937251001010100001010000507079840200182003720037186603187671001020100002030000200372003711100211091010100001000640616561996910000102003820038200382003820038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sha1su0 v0.4s, v8.4s, v9.4s
  movi v1.16b, 0
  sha1su0 v1.4s, v8.4s, v9.4s
  movi v2.16b, 0
  sha1su0 v2.4s, v8.4s, v9.4s
  movi v3.16b, 0
  sha1su0 v3.4s, v8.4s, v9.4s
  movi v4.16b, 0
  sha1su0 v4.4s, v8.4s, v9.4s
  movi v5.16b, 0
  sha1su0 v5.4s, v8.4s, v9.4s
  movi v6.16b, 0
  sha1su0 v6.4s, v8.4s, v9.4s
  movi v7.16b, 0
  sha1su0 v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160205800386000000004925801001008000010080000500640000080019800388003859964359996801002008000020024000080038800381116020110099100100160000100000000000010110116118003501600001008003980039800398003980039
160204800385990000004925801001008000010080000500640000080019800388003859964359996801002008000020024000080038800381116020110099100100160000100000000000010110116118003501600001008003980039800398003980039
160204800385990000004925801001008000010080000500640000080019800388003859964359996801002008000020024000080038800381116020110099100100160000100000000000010110116118003501600001008003980039800398003980039
160204800386000000004925801001008000010080000500640000080019800388003859964359996801002008000020024000080038800381116020110099100100160000100000000000010110116118003501600001008003980039800398003980039
160204800386000000004925801001008000010080000500640000080019800388003859964359996801002008000020024000080038800381116020110099100100160000100000000010010110116118003501600001008003980039800398003980039
1602048003860000000071425801001008000010080000500640000080019800388003859964359996801002008000020024000080038800381116020110099100100160000100000000000010110116118003501600001008003980039800398003980039
1602048003859900000071425801001008000010080000500640000080019800388003859964359996801002008000020024000080038800381116020110099100100160000100000000000010110116118003501600001008003980039800398003980039
160204800386000000004925801231008000010080000500640000080019800388003859964359996801002008000020024000080038800381116020110099100100160000100000003000010110116118003501600001008003980039800398003980039
160204800385990000004925801001008000010080000500640000080019800388003859964359996801002008000020024000080038800381116020110099100100160000100000000000010110116118003501600001008003980039800398003980039
160204800385990000004925801001008000010080000500640000080019800388003859964359996801002008000020024000080038800861116020110099100100160000100000000000010110116218003501600001008003980039800398003980039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)st unit uop (a7)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024800386000000000055258001010800001080000506400001158001980038800385998636001880010208000020240000800388003811160021109101016000010000010022821215622121168003504013160000108003980039800398003980039
160024800385990000000055258001010800001080000506400001158001980038800385998636001880010208000020240000800388003811160021109101016000010000010022821141621113148003502013160000108003980039800398003980039
160024800385990000000055258001010800001080000506400001158001980038800385998636001880010208000020240000800388003811160021109101016000010000310024821141621115148003502013160000108003980039800398003980039
160024800386000000000055258001010800001080000506400001158001980038800385998636001880010208000020240000800388003811160021109101016000010000010022831121621114138003504013160000108003980039800398003980039
1600248003859910000450055258001010800001080000506400001158001980231800385998636001880010208000020240000800388003811160021109101016000010000010022822161621113138003502013160000108003980039800398003980039
160024801365990000000055258001010800001080000506400001158001980038800385998636001880010208000020240000800388003811160021109101016000010000010022112113162219158003502013160000108003980039800878003980039
160024800386000000000072025800101080000108000050640000115800198003880038599863600188001020800002024020180038800381116002110910101600001000001002282113162118168003502013160000108003980039800398003980039
160024800386000000000055258001010800001080000506400001158001980038800385998636001880010208000020240000800388003811160021109101016000010000010022821141621114148003502013160000108003980039800398003980039
160024800386000000000061258001010800001080000506400001158001980038800385998636001880010208000020240000800388003811160021109101016000010000010024831151621215138003514026160000108003980039801848003980039
160024800386000000000011292580010108000010800005064000011580019800388003859986360018800102080000202400008003880038111600211091010160000100000100221122142421114138003502013160000108003980039800398003980039

Test 6: throughput

Count: 16

Code:

  sha1su0 v0.4s, v16.4s, v17.4s
  sha1su0 v1.4s, v16.4s, v17.4s
  sha1su0 v2.4s, v16.4s, v17.4s
  sha1su0 v3.4s, v16.4s, v17.4s
  sha1su0 v4.4s, v16.4s, v17.4s
  sha1su0 v5.4s, v16.4s, v17.4s
  sha1su0 v6.4s, v16.4s, v17.4s
  sha1su0 v7.4s, v16.4s, v17.4s
  sha1su0 v8.4s, v16.4s, v17.4s
  sha1su0 v9.4s, v16.4s, v17.4s
  sha1su0 v10.4s, v16.4s, v17.4s
  sha1su0 v11.4s, v16.4s, v17.4s
  sha1su0 v12.4s, v16.4s, v17.4s
  sha1su0 v13.4s, v16.4s, v17.4s
  sha1su0 v14.4s, v16.4s, v17.4s
  sha1su0 v15.4s, v16.4s, v17.4s
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0002

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020416004011980000001894925160100100160000100160000500128000016001916003816003813996403139996160100200160000200480000160038160038111602011009910010016000010000000010110216221600350160000100160039160039160039160039160039
1602041600381199000000484925160100100160000100160000500128000016001916003816003813996403139996160100200160000200480000160038160038111602011009910010016000010000036450010110216221600350160000100160039160088160039160039160039
160204160038119900000094925160100100160000100160000500128000016001916003816003813996403139996160100200160000200480000160038160038111602011009910010016000010000000010110216221600350160000100160039160039160039160039160039
160204160038119900001104925160100100160000100160000500128000016001916003816003813996403140034160100200160000200480000160038160038111602011009910010016000010002030010110216221600350160000100160039160039160039160039160039
160204160038119900000004925160100100160000100160000500128000016001916003816003813996403139996160100200160000200480000160038160038111602011009910010016000010000000010110216221600350160000100160039160039160039160039160039
16020416003811990000001354925160100100160000100160000500128000016001916003816003813996403139996160100200160000200480000160038160038111602011009910010016000010000000010110216221600350160000100160039160039160039160039160085
1602041600381199000000394925160100100160000100160000500128000016001916003816003813996403139996160100200160000200480144160038160038111602011009910010016000010000000010110216231600350160000100160039160039160039160039160039
160204160038119900000004925160100114160000100160000500128000016001916003816003813996403139996160100200160000200480000160038160038111602011009910010016000010000000010110216221600350160000100160039160039160039160039160039
16020416003811990000007571425160100100160000100160000500128000016001916003816003813996403139996160100200160000200480000160038160038111602011009910010016000010000000010110216221600350160000100160039160039160039160039160039
1602041600381199000000514925160100100160000100160000500128000016001916003816003813996433139996160100200160000200480000160038160038111602011009910010016000010000000110110216221600350160000100160039160039160039160039160039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0002

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002416008711991100607625160010101600001016000050128000011516001916003816003813998603140018160010201600002048000016003816003811160021109101016000010000000000100227118162114516003302016016000010160039160039160087160039160039
16002416003811990000005525160010101600001016000050128000011516001916003816003813998603140018160010201600002048000016003816003811160021109101016000010000000000100228527162215316003302016016000010160039160039160039160039160039
160024160038119800000110325160010101600001016000050128000011516001916003816003813998603140018160010201600002048000016003816003811160021109101016000010030000000100228514162117716003302016016000010160039160039160039160039160039
160024160038119900000061251600101016000010160000501280000115160019160038160038139986026140006160010201600002048000016003816003811160022109101016000010000000000100228515162113616003302016016000010160039160039160039160039160039
16002416003811990000005525160010101600001016000050128000011516001916003816003813998603140018160010201600002048000016003816003811160021109101016000010000000000100228517162114816003302016016000010160039160039160039160039160039
160024160038119900000022625160010101600001016000050128000011516001916003816003813998603140018160010201600002048000016003816003811160021109101016000010000000000100408113162118716003302016016000010160039160039160039160039160039
16002416003811990000005525160010101600001016000050128000011516001916003816003813998603140018160010201600002048000016003816003811160021109101016000010000000000100228518162118816003302016016000010160039160039160039160039160039
1600241600381199000070205525160010101600001016000050128019511516001916003816003813998603140018160010201600002048000016003816003811160021109101016000010000000000100228517162117716003302016016000010160039160039160039160039160085
16002416003811980000005525160010101600001016000050128019511516001916003816003813998603140018160010201600002048000016003816003811160021109101016000010000000000100223517162115816003302016016000010160039160039160039160039160039
160024160038119800000055251600101016000010160000501280000100160019160038160038139986031400181600102016000020480000160038160038111600211091010160000100000000001002285161621716716003302016016000010160039160039160039160039160039