Firestorm: SHA1SU1 measurements

Code:

  sha1su1 v0.4s, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	18	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	3	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	12	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	15	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	3	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  sha1su1 v0.4s, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	1	20018	20037	20037	18638	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	81	710	1	16	1	1	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	1	20018	20037	20037	18638	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	96	710	1	16	1	1	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	1	20018	20037	20037	18638	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	102	710	1	16	1	1	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	251	9937	25	10100	100	10000	100	10000	500	707984	1	20018	20037	20037	18638	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	9	710	1	16	1	1	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	9937	25	10100	100	10000	114	10000	500	707984	1	20018	20037	20037	18638	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	6	710	1	16	1	1	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	1	20018	20037	20037	18638	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	1	20018	20037	20037	18638	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	17	1	1	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	3	0	710	1	16	1	1	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	1	20018	20037	20037	18638	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	16	1	1	19967	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	1	3	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	102	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	82	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10056	20	10000	20	20000	20037	20037	2	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	24	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	9899	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	2	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  sha1su1 v0.4s, v0.4s

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	61	9936	25	10100	100	10000	100	10000	500	707921	1	20018	20084	20037	18644	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	3	1	1	1	717	1	16	0	2	19965	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	9936	25	10100	100	10000	100	10000	500	707921	0	20018	20037	20037	18644	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	0	16	0	0	19978	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	9936	25	10100	100	10000	100	10000	500	707921	0	20018	20037	20037	18644	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	718	0	16	0	0	19978	10000	100	20038	20038	20038	20038	20038
10204	20037	149	0	0	726	9936	25	10100	100	10000	100	10000	500	707921	1	20018	20037	20037	18644	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	718	0	16	0	0	19978	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	944	9936	25	10100	100	10000	100	10000	500	707921	0	20018	20037	20037	18644	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	718	0	16	0	0	19979	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	212	9936	25	10100	100	10000	100	10000	500	707921	1	20018	20037	20037	18644	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	0	16	0	0	19978	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	124	9936	25	10100	100	10000	100	10000	500	707921	1	20018	20037	20037	18644	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	0	16	0	0	19979	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	103	9936	25	10100	100	10000	100	10000	500	707921	1	20018	20037	20037	18644	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	718	0	16	0	0	19979	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	9936	25	10100	100	10000	100	10000	500	707921	0	20018	20037	20037	18644	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	718	0	16	0	0	19978	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	533	9936	25	10100	100	10000	100	10000	500	707921	0	20018	20037	20037	18644	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	718	0	16	0	0	19978	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	458	9936	25	10010	10	10000	10	10000	50	707921	0	20018	20037	20037	18659	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19968	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	9936	25	10010	10	10000	10	10000	50	707921	0	20018	20037	20037	18659	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	1	0	640	2	16	2	2	19968	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	9936	25	10010	10	10000	10	10000	50	707921	0	20018	20037	20037	18659	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	2	0	640	2	16	2	2	19968	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	126	9936	25	10010	10	10000	10	10000	50	707921	0	20018	20037	20037	18659	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19968	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	9936	25	10010	10	10000	10	10000	50	707921	0	20018	20037	20037	18659	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	25	6	640	2	16	2	2	19968	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	163	9936	25	10010	10	10000	10	10000	50	707921	0	20018	20037	20037	18659	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19968	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	166	9936	25	10010	10	10000	10	10000	50	707921	0	20018	20037	20037	18659	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19968	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	168	9936	25	10010	10	10000	10	10000	50	707921	0	20018	20037	20037	18659	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19968	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	168	9936	25	10010	10	10000	10	10000	50	707921	0	20018	20037	20037	18659	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19968	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	189	9936	25	10010	10	10000	10	10000	50	707921	0	20018	20037	20037	18659	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19968	0	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sha1su1 v0.4s, v8.4s
  movi v1.16b, 0
  sha1su1 v1.4s, v8.4s
  movi v2.16b, 0
  sha1su1 v2.4s, v8.4s
  movi v3.16b, 0
  sha1su1 v3.4s, v8.4s
  movi v4.16b, 0
  sha1su1 v4.4s, v8.4s
  movi v5.16b, 0
  sha1su1 v5.4s, v8.4s
  movi v6.16b, 0
  sha1su1 v6.4s, v8.4s
  movi v7.16b, 0
  sha1su1 v7.4s, v8.4s

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	80039	600	0	0	0	0	0	0	575	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	59970	6	59991	80100	200	80008	200	160016	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10117	0	16	0	0	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	599	0	0	0	0	0	0	1812	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	59970	6	59991	80100	200	80008	200	160016	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10117	0	16	0	0	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	599	0	0	0	0	0	0	321	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	59970	6	60021	80100	200	80008	200	160016	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10132	0	16	0	0	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	599	0	0	0	0	0	0	2208	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	59970	6	59991	80100	200	80008	200	160016	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10117	0	16	0	0	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	599	0	0	0	0	0	0	2101	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	59970	6	59991	80100	200	80008	200	160016	80038	80038	1	1	160201	100	99	100	100	160000	100	2	0	0	0	1	1	1	10117	0	16	0	0	80035	0	160000	100	80039	80087	80087	80087	80185
160204	80038	599	0	0	0	0	21	0	38	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	59970	6	59991	80100	200	80008	200	160016	80038	80038	1	1	160201	100	99	100	100	160000	100	0	1	3	2	1	1	1	10117	0	24	0	0	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	600	0	0	0	0	0	0	80	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	59970	6	59991	80100	200	80008	200	160016	80038	80038	1	1	160201	100	99	100	100	160000	100	0	1	0	0	1	1	1	10117	0	16	0	0	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	600	0	0	0	0	0	0	453	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	59970	6	59991	80100	200	80008	200	160016	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10117	0	16	0	0	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	599	0	0	0	0	0	0	2411	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	59970	6	59991	80100	200	80008	200	160016	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10117	0	16	0	0	80035	0	160000	100	80039	80039	80039	80087	80039
160204	80038	599	0	0	0	0	3	0	80	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	59970	6	59991	80100	200	80008	200	160016	80038	80038	1	1	160201	100	99	100	100	160000	100	0	1	3	0	1	1	1	10117	0	16	0	0	80035	0	160000	100	80039	80039	80097	80039	80039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	80039	599	0	0	0	17	323	25	80010	10	80000	10	80000	50	640000	0	1	80019	80038	80038	59986	3	60018	80010	20	80000	20	160000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10024	6	2	2	9	16	4	2	2	4	3	80093	20	13	160000	10	80039	80039	80039	80039	80039
160024	80038	599	0	0	0	17	191	25	80010	10	80000	10	80000	50	640000	0	1	80019	80038	80038	59986	3	60018	80010	20	80000	20	160000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	3	0	0	10024	3	2	2	4	16	4	2	2	4	4	80035	40	26	160000	10	80039	80039	80039	80039	80039
160024	80038	600	0	0	0	13	912	25	80010	10	80000	10	80000	50	640000	0	1	80019	80038	80038	59986	3	60018	80010	20	80000	20	160000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10024	6	1	2	3	16	2	2	2	3	4	80035	20	26	160000	10	80039	80039	80039	80039	80096
160024	80038	600	0	0	0	15	210	25	80010	10	80000	10	80000	50	640000	0	1	80019	80038	80038	59986	3	60018	80010	20	80000	20	160000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10024	6	2	2	3	16	4	2	2	3	4	80035	20	13	160000	10	80039	80039	80039	80039	80039
160024	80038	599	0	0	0	14	55	25	80010	10	80000	10	80000	50	640000	1	1	80019	80038	80038	59986	3	60018	80010	20	80000	20	160000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	4	0	0	0	10022	3	1	1	7	16	2	1	1	4	4	80035	20	13	160000	10	80039	80039	80039	80039	80039
160024	80038	599	0	0	0	17	55	25	80010	10	80000	10	80000	50	640000	1	1	80019	80038	80038	59986	3	60018	80010	20	80000	20	160000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	3	1	565	0	0	10022	3	1	1	4	16	2	1	1	4	3	80145	20	13	160000	10	80039	80039	80039	80183	80087
160024	80086	599	1	177	88	13	736	81	80056	10	80023	10	80050	50	640390	1	1	80019	80038	80038	59986	3	60018	80010	20	80000	20	160000	80038	80087	1	1	160021	10	9	10	10	160000	10	2	2	0	0	9	0	0	10022	3	1	1	4	16	2	1	1	6	4	80035	20	13	160000	10	80039	80039	80039	80039	80039
160024	80038	600	0	0	0	15	78	25	80010	10	80000	10	80000	50	640000	1	1	80019	80038	80038	59986	3	60018	80010	20	80000	20	160000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10045	3	1	1	5	16	2	1	1	7	6	80035	20	13	160000	10	80039	80039	80039	80039	80039
160024	80038	600	0	0	0	18	553	25	80010	10	80000	10	80000	50	640000	1	1	80019	80038	80038	59986	3	60018	80010	20	80000	20	160000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	3	1	1	4	16	2	1	1	7	6	80035	20	13	160000	10	80039	80039	80039	80039	80039
160024	80038	599	0	0	0	16	55	25	80010	10	80000	10	80000	50	640000	1	1	80019	80038	80038	59986	3	60060	80010	20	80000	20	160000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	3	1	1	6	16	2	1	1	7	7	80035	20	13	160000	10	80039	80039	80039	80039	80039

Test 5: throughput

Count: 16

Code:

  sha1su1 v0.4s, v16.4s
  sha1su1 v1.4s, v16.4s
  sha1su1 v2.4s, v16.4s
  sha1su1 v3.4s, v16.4s
  sha1su1 v4.4s, v16.4s
  sha1su1 v5.4s, v16.4s
  sha1su1 v6.4s, v16.4s
  sha1su1 v7.4s, v16.4s
  sha1su1 v8.4s, v16.4s
  sha1su1 v9.4s, v16.4s
  sha1su1 v10.4s, v16.4s
  sha1su1 v11.4s, v16.4s
  sha1su1 v12.4s, v16.4s
  sha1su1 v13.4s, v16.4s
  sha1su1 v14.4s, v16.4s
  sha1su1 v15.4s, v16.4s

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0002

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	160039	1199	0	0	3	0	0	0	0	41	25	160100	100	160000	100	160000	500	1280000	0	160019	160038	160038	139971	6	139992	160350	200	160008	200	320298	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10117	0	0	16	0	0	160035	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	3	0	0	0	38	25	160100	100	160000	100	160000	500	1280000	0	160019	160038	160038	139971	6	139992	160100	200	160008	200	320016	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10117	0	0	16	1	0	160035	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	0	0	0	703	25	160100	100	160000	100	160000	500	1280000	0	160019	160038	160038	139971	6	139992	160100	200	160008	200	320016	160038	160038	5	1	160201	100	99	100	100	160000	100	2	0	0	0	0	9	0	1	1	1	10117	0	0	16	0	0	160035	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	1	0	0	0	0	0	0	38	25	160100	100	160000	100	160000	500	1280000	0	160019	160038	160038	139971	6	139992	160100	200	160008	200	320016	160086	160086	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10117	0	0	16	0	0	160035	160000	100	160039	160039	160039	160039	160039
160204	160038	1198	0	0	0	0	0	0	0	38	25	160100	100	160000	100	160000	500	1280000	1	160019	160038	160038	139971	6	139992	160100	200	160008	200	320016	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10170	0	0	16	0	0	160083	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	1	0	0	0	0	0	38	25	160100	100	160000	100	160000	500	1280000	1	160019	160038	160038	139971	6	140132	160100	200	160008	200	320016	160038	160230	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	3	0	1	1	1	10173	0	0	16	0	0	160035	160000	100	160039	160039	160039	160229	160039
160204	160232	1199	0	0	0	0	0	0	0	38	25	160100	100	160000	100	160000	500	1280000	0	160019	160038	160184	139971	6	139992	160100	200	160008	200	320016	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	4	2	0	0	1	1	1	10117	0	0	16	0	0	160035	160000	100	160039	160039	160039	160039	160039
160204	160038	1200	0	0	0	0	39	0	0	703	25	160100	100	160000	100	160000	500	1280000	1	160019	160038	160038	139971	6	139992	160100	200	160008	200	320016	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	3	0	1	1	1	10117	0	0	16	0	0	160035	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	1	0	0	0	0	0	38	25	160100	100	160000	100	160000	500	1280000	1	160019	160038	160038	139971	6	139992	160100	200	160008	200	320016	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	3	0	0	0	1	1	1	10117	0	0	16	0	0	160035	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	1	0	0	0	0	0	0	38	25	160100	100	160000	100	160000	500	1280000	0	160019	160038	160038	139971	6	139992	160100	200	160008	200	320016	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10117	0	0	16	0	1	160035	160000	100	160039	160039	160039	160039	160039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0002

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	160039	1199	0	55	42	160010	10	160000	10	160000	50	1280000	1	1	5	160019	0	160232	160038	139986	3	140018	160010	20	160000	20	320000	160038	160182	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	2	1	22	16	2	1	1	19	9	160033	15	13	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	735	25	160010	10	160000	10	160000	50	1280000	1	1	5	160019	0	160038	160038	139986	3	140018	160010	20	160000	20	320000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	2	1	19	16	2	1	1	19	9	160033	15	13	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	9	55	25	160010	10	160000	10	160000	50	1280000	1	1	0	160019	0	160038	160038	139986	3	140018	160010	20	160000	20	320000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	2	1	19	16	2	1	1	19	19	160033	15	13	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	720	25	160010	10	160000	10	160000	50	1280000	1	1	5	160019	0	160038	160038	139986	3	140018	160010	20	160000	20	320000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	2	1	9	16	2	1	1	9	16	160083	15	26	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	61	25	160010	10	160000	10	160000	50	1280000	1	1	5	160019	3	160038	160038	139986	3	140018	160010	20	160000	20	320000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	53	0	0	0	0	10022	8	3	2	9	16	4	2	2	9	19	160033	30	26	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	55	25	160010	10	160000	10	160000	50	1280000	1	1	5	160019	0	160038	160038	139986	3	140018	160010	20	160033	20	320000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	2	1	19	16	2	1	1	19	19	160033	15	13	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	36	55	25	160010	10	160000	10	160000	50	1280000	1	1	5	160019	0	160038	160038	139986	3	140018	160010	20	160000	20	320000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	1	0	0	0	0	10022	8	2	1	9	16	2	1	1	19	19	160033	30	26	160000	10	160039	160039	160039	160039	160039
160024	160038	1198	0	55	80	160010	10	160000	10	160000	50	1280000	1	1	5	160019	0	160038	160038	139986	3	140018	160010	20	160000	20	320000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	3	2	19	16	4	2	2	19	15	160033	30	26	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	55	25	160010	10	160000	10	160000	50	1280195	1	1	5	160019	0	160038	160038	139986	3	140018	160010	20	160000	20	320000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10024	11	3	2	19	16	4	2	2	19	19	160033	30	26	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	726	175	160010	10	160000	10	160050	50	1280000	0	1	5	160019	0	160197	160038	139986	3	140018	160035	20	160000	20	320202	160231	160038	1	1	160021	10	9	10	10	160000	10	1	0	2878	0	0	0	10024	11	3	2	7	16	4	2	2	9	19	160033	30	26	160000	10	160039	160039	160039	160039	160039

SHA1SU1

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations